LA-ISPPAC-POWR1014-01TN48E Lattice, LA-ISPPAC-POWR1014-01TN48E Datasheet
LA-ISPPAC-POWR1014-01TN48E
Specifications of LA-ISPPAC-POWR1014-01TN48E
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LA-ISPPAC-POWR1014-01TN48E Summary of contents
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... TQFP package, lead-free option © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice ...
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... CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µ seconds. The CPLD is programmed using Logi- Builder™, an easy-to-learn language integrated into the PAC-Designer monitor the status of any of the analog input channel comparators or the digital inputs ...
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... Open Drain Output 1 OUT14 Open Drain Output 8 40 RESETb Digital I/O 42 PLDCLK Digital Output LA-ispPAC-POWR1014/A Automotive Family Data Sheet Voltage Range 1, 2 VCCINP PLD Logic Input 1 Registered by MCLK 1, 3 VCCINP PLD Logic Input 2 Registered by MCLK 1, 3 VCCINP PLD Logic Input 3 Registered by MCLK ...
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... VCCD and VCCA pins must be connected together on the circuit board. 7. Open-drain outputs require an external pull-up resistor to a supply. 8. The RESETb pin should only be used for cascading two or more LA-ispPAC-POWR1014/A devices. 9. These pins should be connected to GNDD (LA-ispPAC-POWR1014 device only). LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... CCINP CCINP I JTAG supply current CCJ I Core and analog supply current CCPROG 1. Includes currents on V and V CCD CCA LA-ispPAC-POWR1014/A Automotive Family Data Sheet Parameter Conditions HVOUT[1:2] OUT[3:14] Conditions 2 During E programming pins OUT[3:14] pins HVOUT[1:2] pins in open-drain mode Power applied ...
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... IN V Range Programmable trip-point range MON V Sense Near-ground sense threshold Z V Accuracy Absolute accuracy of any trip-point MON Hysteresis of any trip-point (relative to HYST setting) 1. Guaranteed by characterization across V High Voltage FET Drivers Symbol Parameter V Gate driver output voltage PP Gate driver source current I OUTSRC ...
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... Threshold above which RESETb is HIGH TH V Threshold above which RESETb is valid T Minimum duration dropout required to trigger T POR RESETb Capacitive load on RESETb for master/slave C L operation 1. Corresponds to VCCA and VCCD supply voltages. LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions 2 Time from I C request ...
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... PLDCLK output frequency PLDCLK Timers Range of programmable Timeout Range timers (128 steps) Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 8 Min. ...
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... IN[1:4] referenced TDO, TDI, TMS, ATDI, TDISEL referenced to V CCINP 2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded. LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions HVOUT[1:2] in open drain mode and pulled ...
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... CONVERT readout. When F is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit. I2C LA-ispPAC-POWR1014/A Automotive Family Data Sheet 1 Definition 10 100KHz 400KHz Min ...
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... CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 3. Programming Timing Diagram VIH TMS VIL t t SU1 H t CKH VIH TCK VIL State Update-IR LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH ...
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... Theory of Operation Analog Monitor Inputs The LA-ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 6. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘ ...
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... Lattice Semiconductor Figure 6. LA-ispPAC-POWR1014/A Voltage Monitors VMONx Trip Point A Trip Point B Analog Input Figure 6 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. ...
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... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. LA-ispPAC-POWR1014/A Automotive Family Data Sheet UTP LTP ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet Coarse Range Setting 1.360 1.612 1.923 2.290 1.353 1.603 1.913 2.278 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2.254 1 ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2.254 1.331 1.578 1.883 2.242 1.324 1.570 1.873 2.230 1.317 1.561 1 ...
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... The third section in the LA-ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the com- parator output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16µ ...
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... A microcontroller can place a request for any VMON voltage measurement at any time through the I PAC-POWR1014A only). Upon the receipt VMON through the ADC MUX. The ADC output is then latched into the I ...
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... GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the LA-ispPAC-POWR1014/A device. The output signals of the LA-ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 9. GLB3 generates timer control ...
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... Oscillator 8MHz The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer clocks also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir- LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing SW2. Each of the four timers provides independent timeout intervals ranging from 32µs to 1.96 seconds in 128 steps ...
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... The maximum voltage that the output level at the pin will rise to is also programmable. The HVOUT pin source current, which is programmable between 12.5 µA and 100 µA, is used to control the FET turn-on rate. Similarly, the HVOUT sink current, which is programmable between 3000 µA and 100 µA, is used to control the turn-off rate. ...
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... C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas- ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The LA-ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers. ...
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... SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format. ...
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... VMON_STATUS2 (Read Only also possible to directly read the value of the voltage present on any of the VMON inputs by using the LA-isp- PAC-POWR1014A’s ADC. Three registers provide the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Description R VMON input status Vmon[4:1] R VMON input status Vmon[8:5] ...
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... When the conversion is complete, the result may be read out of the ADC by 2 performing two I C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH recom- 2 mended that the I C master load a second conversion command only after the completion of the current conversion LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... To insure every ADC conversion result is valid, preferred operation is to clock I DONE bit status or wait for the full T request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The status of the digital input lines may also be monitored and controlled through I ...
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... OUTPUT_STATUS0 (Read Only) OUT8 OUT7 b7 b6 0x04 - OUTPUT_STATUS1 (Read Only 0x0E - GP_OUTPUT1 (Read/Write) GP8 GP7 b7 b6 0x0F - GP_OUTPUT2 (Read/Write The UES word may also be read through the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Configuration MUX 14 14 Output_Status0 Output_Status1 Interface Unit OUT6 OUT5 OUT4 ...
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... The I C interface also provides the ability to initiate reset operations. The LA-ispPAC-POWR1014A may be reset by issuing a write of any value to the I equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...
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... After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the LA-ispPAC-POWR1014A. As part of the service func- tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function ...
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... PAC-POWR1014/A elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When com- pleted, confi ...
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... JTAG signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the LA-ispPAC-POWR1014/A are connected to the header as shown in Figure 26. Note: The LA-ispPAC-POWR1014/A should be the last device in the JTAG chain. ...
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... VCCD and VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the LA-ispPAC-POWR1014/A is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOS- FET driver are driven low, and all other inputs are ignored ...
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... LA-ispPAC-POWR1014/A can be verified using an ispPAC-POWR1220AT8 engineering prototype board connected to the parallel port with a Lattice ispDOWNLOAD strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro- cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in LA- ispPAC-POWR1014/A for a given application ...
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... In a given state, the controller responds according to the level on the TMS input as shown in Figure 30. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register ...
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... The LA-ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. Table 11 lists the instructions supported by the LA-ispPAC-POWR1014/A JTAG Test Access Port (TAP) controller: ...
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... The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The LA-ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 11. ...
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... TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (Figure 31). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device issuing a Test-Logic-Reset instruction. The bit code for this instruction is defi ...
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... OUTPUTS_HIGHZ. OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAM_ENABLE – This instruction enables the programming mode of the LA-ispPAC-POWR1014/A. This instruction also forces the outputs into the OUTPUTS_HIGHZ. IDCODE – ...
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... Lattice Semiconductor PROGRAM_DONE_BIT – This instruction sets the ‘Done’ bit, which enables the LA-ispPAC-POWR1014/A sequence to start. RESET – This instruction resets the PLD sequence and output macrocells. IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input ‘IN1.’ The PLD input has to be con- fi ...
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... SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS. 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. ...
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... Lattice Semiconductor Part Number Description LA-ispPAC-POWR1014X - 01TN48E Device Family Device Number ADC Support A = ADC present LA-ispPAC-POWR1014/A Ordering Information Lead-Free Packaging Part Number LA-ispPAC-POWR1014A-01TN48E LA-ispPAC-POWR1014-01TN48E Package Options OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com Revision History Date Version January 2008 01.0 LA-ispPAC-POWR1014/A Automotive Family Data Sheet LA-ispPAC-POWR1014 6 48-Pin TQFP Change Summary Initial release. 43 ...