LA-ISPPAC-POWR1014A-01TN48E Lattice, LA-ISPPAC-POWR1014A-01TN48E Datasheet
LA-ISPPAC-POWR1014A-01TN48E
Specifications of LA-ISPPAC-POWR1014A-01TN48E
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LA-ISPPAC-POWR1014A-01TN48E Summary of contents
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... Direct input control © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice ...
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... CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µ seconds. The CPLD is programmed using Logi- Builder™, an easy-to-learn language integrated into the PAC-Designer monitor the status of any of the analog input channel comparators or the digital inputs ...
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... Lattice Semiconductor Pin Descriptions Number Name Pin Type 44 IN1 Digital Input 46 IN2 Digital Input 47 IN3 Digital Input 48 IN4 Digital Input 25 VMON1 Analog Input 26 VMON2 Analog Input 27 VMON3 Analog Input 28 VMON4 Analog Input 32 VMON5 Analog Input 33 VMON6 Analog Input 34 VMON7 Analog Input ...
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... Lattice Semiconductor Pin Descriptions (Cont.) Number Name Pin Type 42 PLDCLK Digital Output 43 MCLK Digital I/O 21 TDO Digital Output 22 TCK Digital Input 16 TMS Digital Input 18 TDI Digital Input 17 ATDI Digital Input 19 TDISEL Digital Input SCL Digital Input SDA Digital I/O 1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied to GNDD ...
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... Lattice Semiconductor Absolute Maximum Ratings Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent dam- age to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied. ...
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... Gate driver output voltage PP Gate driver source current I OUTSRC (HIGH state) Gate driver sink current I OUTSINK (LOW state) 1. 12V setting only available on ispPAC-POWR1014-02 and ispPAC-POWR1014A-02. Conditions During programming cycle supplies. Conditions 1 range, operating temperature, process. CCA Conditions 1 12V setting ...
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... Power-on reset to valid VMON comparator T GOOD output and AGOOD is true Minimum duration brown out required to T BRO trigger RESETb T Delay from brown out to reset state. POR V Threshold below which RESETb is LOW TL V Threshold above which RESETb is HIGH TH V Threshold above which RESETb is valid ...
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... Lattice Semiconductor Figure 2-2. ispPAC-POWR1014/A Power-On Reset Reset State T BRO T T RST POR Start Up State T START Analog Calibration T GOOD 2-8 ispPAC-POWR1014/A Data Sheet VCC RESETb MCLK PLDCLK AGOOD (Internal) ...
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... Lattice Semiconductor AC/Transient Characteristics Symbol Parameter Voltage Monitors Propagation delay input to t PD16 output glitch filter OFF Propagation delay input to t PD64 output glitch filter ON Oscillators Internal master clock f CLK frequency (MCLK) Externally applied master f CLKEXT clock (MCLK) f PLDCLK output frequency ...
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... Lattice Semiconductor Digital Specifications Symbol Parameter I ,I Input leakage, no pull-up/pull-down Output leakage current OH-HVOUT Input pull-up current (TMS, TDI, I TDISEL, ATDI, MCLK, PLDCLK, PU RESETb) V Voltage input, logic low IL V Voltage input, logic high IH HVOUT[1:2] (open drain mode), V OUT[3:14] OL TDO, MCLK, PLDCLK, SDA ...
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... Lattice Semiconductor Port Characteristics Symbol clock/data rate After start SU;STA T After start HD;STA T Data setup SU;DAT T Stop setup SU;STO T Data hold; SCL= Vih_min = 2.1V HD;DAT T Clock low period LOW T Clock high period HIGH T Fall time; 2.25V to 0.65V F T Rise time; 0.65V to 2.25V ...
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... Lattice Semiconductor Timing for JTAG Operations Symbol Parameter t Program enable delay time ISPEN t Program disable delay time ISPDIS t High voltage discharge time, program HVDIS t High voltage discharge time, erase HVDIS t Falling edge of TCK to TDO active CEN t Falling edge of TCK to TDO disable ...
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... Lattice Semiconductor Figure 2-5. Verify Timing Diagram VIH TMS VIL SU1 H SU1 t t CKH CKL VIH TCK VIL State Update-IR Figure 2-6. Discharge Timing Diagram VIH TMS VIL SU1 H SU1 t t CKH CKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase or Program) ...
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... Lattice Semiconductor Figure 2-7. ispPAC-POWR1014/A Voltage Monitors VMONx Trip Point A Trip Point B Analog Input Figure 2-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. ...
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... Lattice Semiconductor Figure 2-8. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output, (b) Corresponding to Upper and Lower Trip Points Comparator Logic Output During power supply ramp-up the comparator output changes from logic when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state when the power supply voltage crosses the lower trip point (LTP) ...
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... Lattice Semiconductor Table 2-1. Trip Point Table Used For Over-Voltage Detection Fine Range Setting 0.806 0.960 1.143 2 0.802 0.955 1.137 3 0.797 0.950 1.131 4 0.793 0.945 1.125 5 0.789 0.940 1.119 6 0.785 0.935 1.113 7 0.781 0.930 1.107 8 0.776 0.925 1.101 9 0.772 0.920 1.095 10 0 ...
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... Lattice Semiconductor Table 2-2. Trip Point Table Used For Under-Voltage Detection Fine Range Setting 0.797 0.950 1.131 2 0.793 0.945 1.125 3 0.789 0.940 1.119 4 0.785 0.935 1.113 5 0.781 0.930 1.107 6 0.776 0.925 1.101 7 0.772 0.920 1.095 8 0.768 0.915 1.089 9 0.764 0.910 1.083 10 0 ...
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... The third section in the ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the compara- tor output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16µ ...
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... A microcontroller can place a request for any VMON voltage measurement at any time through the I (ispPAC-POWR1014A only). Upon the receipt of an ADCMUX selection command, the ADC will be connected to the selected VMON through the ADC MUX. The ADC output is then latched into the I ...
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... OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the com- mon PLD clock that is generated by dividing the 8 MHz master clock by 32 ...
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... Internal Oscillator 8MHz The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer clocks also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir- Global Reset ...
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... A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing SW2. Each of the four timers provides independent timeout intervals ranging from 32µs to 1.96 seconds in 128 steps ...
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... Lattice Semiconductor Figure 2-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode Charge Pump (6 to 12V Digital Control from PLD Digital Control from I (ispPAC-POWR1014A Only) 1. -01 performance grade devices provide three selectable output voltage settings from 6V to 10V in 2V steps. The -02 performance grade devices also support the 12V output voltage setting ...
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... C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas- ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers. ...
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... SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format. ...
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... Table 2-7 provides a summary of these registers R/W ACK ACK D7 R/W 2-26 ispPAC-POWR1014/A Data Sheet ACK REGISTER ADDRESS (8 BITS ACK READ DATA (8 BITS) OPTIONAL Note: Shaded Bits Asserted by Slave 2 C interface. These registers STOP STOP ...
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... Lattice Semiconductor 2 Table 2- Control Registers Register Register Address Name Read/Write 0x00 vmon_status0 0x01 vmon_status1 0x02 vmon_status2 0x03 output_status0 0x04 output_status1 0x06 input_status 0x07 adc_value_low 0x08 adc_value_high 0x09 adc_mux 0x0A UES_byte0 0x0B UES_byte1 0x0C UES_byte2 0x0D UES_byte3 0x0E gp_output1 0x0F gp_output2 0x11 ...
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... Lattice Semiconductor Figure 2-19. ADC Interface Registers 0x07 - ADC_VALUE_LOW (Read Only 0x08 - ADC_VALUE_HIGH (Read Only) D11 D10 b7 b6 0x09 - ADC_MUX (Read/Write perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be set using the attenuator 2.048V and 0 - 6.144V. Table 2-8 shows the input attenuator settings. ...
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... To insure every ADC conversion result is valid, preferred operation is to clock I DONE bit status or wait for the full T request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The status of the digital input lines may also be monitored and controlled through I ...
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... Lattice Semiconductor but is not pulled up, the output status bit corresponding with that pin will read ‘1’, but a high output signal will not appear on the pin. Digital outputs may also be optionally controlled directly by the I may be driven either from the PLD output or from the contents of the GP_OUTPUT[1:0] registers with the choice ...
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... Lattice Semiconductor 2 Figure 2-22 Register Mapping for UES Bits 0x0A - UES_BYTE0 (Read Only) UES7 UES6 b7 b6 0x0B - UES_BYTE1 (Read Only) UES15 UES14 b7 b6 0x0C - UES_BYTE2 (Read Only) UES23 UES22 b7 b6 0x0D - UES_BYTE3 (Read Only) UES31 UES30 The I C interface also provides the ability to initiate reset operations. The ispPAC-POWR1014A may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip ...
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... SMBus Standard Configuration) OUT3/SMBA Mode Select (E 2 Configuration) MUX MUX SMBAlert Logic 2 C write) to Low ACK A6 R/W ALERT RESPONSE ADDRESS (0001 100) 2-32 ispPAC-POWR1014/A Data Sheet OUT3/SMBA ACK SLAVE ADDRESS (7 BITS) SLAVE RELEASES SMBA Note: Shaded Bits Asserted by Slave STOP ...
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... POWR1014/A elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, con- figurations can be saved, simulated, and downloaded to devices ...
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... In order to use this feature the JTAG signals of the ispPAC-POWR1014/A are connected to the header as shown in Figure 2-27. Note: The ispPAC-POWR1014/A should be the last device in the JTAG chain. After programming, the VCCPROG pin MUST be left floating before applying power to the VCCD and VCCA pins. ...
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... L Please refer to AN6068, Programming the ispPAC-POWR1220AT8 in a JTAG Chain Using note includes specific SVF code examples and information on the use of Lattice design tools to verify device oper- ation in alternate TDI mode. VCCPROG Power Supply Pin Because the VCCPROG pin directly powers the on-chip programming circuitry, the ispPAC-POWR1014/A device can be programmed by applying power to the VCCPROG pin (without powering the entire chip though the VCCD and VCCA pins) ...
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... PC with a Lattice ispDOWNLOAD™ cable. The board demon- strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro- cess. Input and output connections are provided to aid in the evaluation of the functionality implemented in ispPAC- POWR1014/A for a given application ...
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... In a given state, the controller responds according to the level on the TMS input as shown in Figure 2-31. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic- Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction- Register ...
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... Lattice Semiconductor Figure 2-31. TAP States Test-Logic-Rst Run-Test/Idle Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state ...
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... The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 2-11. ispPAC-POWR1014/A Data Sheet ...
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... TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (Figure 2-32). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 2-11 ...
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... OUTPUTS_HIGHZ. OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAM_ENABLE – This instruction enables the programming mode of the ispPAC-POWR1014/A. This instruction also forces the outputs into the OUTPUTS_HIGHZ. IDCODE – ...
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... Lattice Semiconductor Figure 2-34. UES Register Bit Bit Bit Bit Bit UES_PROGRAM – This instruction will program the content of the UES Register into the UES E The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ...
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... Bytes 2-1 control/read output pins/status VMON Status Registers Byte 9, Byte 8 and Byte 7: Byte 9 is the most significant byte and is shifted out last, ending with bit 71, VMON1A. These bytes consist of the status of VMONxA and VMONxB comparators corresponding to VMON1 through VMON10 inputs. In the following tables, the number in the parenthesis indicates the bit position within the I2C_Data_Register Packet ...
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... Lattice Semiconductor Figure 2-36. VMON Status Registers Byte 9 – VMON_STATUS0 (Read Only, Most Significant), I VMON1A VMON1B (71) (70) Byte 8 – VMON_STATUS1 (Read Only), I VMON5A VMON5B (63) (62) Byte 7 – VMON_STATUS2 (Read Only), I VMON9A VMON9B (55) (54) ADC Interface Registers Byte 6, Byte 5: These bytes contain 12-bit ADC measured values. ...
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... Lattice Semiconductor During the I2C_Data_Register read operation - When I2C_Control_Register bit and bit the Byte 3 value will return INPUT_VALUE register. Byte 3 – INPUT_VALUE (Read operation) – When I2C_Control_Register Bit 5=0 and Bit 4= (23) (22) (21) During the I2C_Data_Register read operation - When I2C_Control_Register bit and bit Byte 3 value will return INPUT_STATUS register. Byte 3 – ...
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... Lattice Semiconductor Figure 2-41. Output Status and GP_Output Registers, Byte 1 Byte 1 – GP_OUTPUT2 (Write Operation) – When I2C_Control_Register Bit 1=1, Bit 0=0, I GP9 GP10 GP11 (7) (6) (5) Byte 1 – GP_OUTPUT2 (Read Operation) – When I2C_Control_Register Bit 1=0, Bit 0=0, I GP9 GP10 GP11 ...
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... Lattice Semiconductor Table 2-13 shows the bit values of 72-bit I2C_Data_Register packet after POR. Table 2-13. I2C_Data_Register Packet Reset Values 2 JTAG Equivalent I C Byte Register Address Register Name 9 0x00 vmon_status0 8 0x01 vmon_status1 7 0x02 vmon_status2 2 0x03 output_status0 1 0x04 output_status1 3 0x06 input_status 6 0x07 adc_value_low ...
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... SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS. 5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. ...
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... Lattice Semiconductor Part Number Description ispPAC-POWR1014X - 0XXX48X Device Family Device Number ADC Support A = ADC present ispPAC-POWR1014/A Ordering Information Conventional Packaging Part Number ispPAC-POWR1014A-01T48I ispPAC-POWR1014-01T48I ispPAC-POWR1014A-02T48I ispPAC-POWR1014-02T48I Lead-Free Packaging Part Number ispPAC-POWR1014A-01TN48I ispPAC-POWR1014-01TN48I ispPAC-POWR1014A-02TN48I ispPAC-POWR1014-02TN48I ispPAC-POWR1014/A Data Sheet Operating Temperature Range I = Industrial (-40 ...
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... Lattice Semiconductor Package Options OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014A 6 48-Pin TQFP 2-50 ispPAC-POWR1014/A Data Sheet 36 VMON9 35 VMON8 34 VMON7 VMON6 33 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...
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... Lattice Semiconductor Package Options (Cont.) OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014/A Data Sheet ispPAC-POWR1014 6 48-Pin TQFP 2-51 36 VMON9 35 VMON8 34 VMON7 33 VMON6 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...
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... Pin Descriptions table: “InxP” changed to “Inx”, “MONx” to “VMONx”, VMON upper range from “5.75V” to “5.87V”. Pin Descriptions table, note 4 - clarification for un-used VMON pins to be tied to GNDD. Absolute Maximum Ratings table and Recommended Operating Conditions table: “ ...