ISL36111DRZ-T7 Intersil, ISL36111DRZ-T7 Datasheet - Page 4

• Manufacturer Part Number: ISL36111DRZ-T7
• Description: IC EQUALIZER REC 11.1GBPS 16QFN
• Manufacturer: Intersil
• Series: QLx™r

Specifications of ISL36111DRZ-T7

• Applications: Data Transport
• Voltage - Supply: 1.1 V ~ 1.3 V
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Mounting Type: Surface Mount
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Other names: ISL36111DRZ-T7TR; QLX111RIQT7; QLX111RIQT7-TR; QLX111RIQT7-TR

Electrical Specifications
NOTES:
10. Limits established by characterization and are not production tested.
11. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
12. Measured using a PRBS 2
13. Rise and fall times measured using a 2GHz clock with a 20ps edge rate.
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched
into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable
through another adapter card. The ISL36111 output signal is then visualized on a scope to determine signal integrity
parameters such as jitter.
Output Transition Time
Propagation Delay
6. The input pins IN[P,N] are DC biased to V
7. Maximum Reflection Coefficient given by equation SDDXX(dB) = -12 + 2*√(f), with f in GHz. Established by characterization
8. Maximum Reflection Coefficient given by equation SDDXX(dB) = -6.3 + 13Log10(f/5.5), with f in GHz. Established by
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not
Generator
not production tested, and is valid so long as the voltages at the input pins IN[P,N] do not violate the voltage ranges specified
in “Absolute Maximum Ratings” on page 3.
and not production tested.
characterization and not production tested.
production tested.
signal (as measured at the input to the channel). Total jitter (T
media-induced loss only.
Pattern
PARAMETERS
Adapter
SMA
Card
FIGURE 3. ISL36111 10.3125Gb/s OUTPUT FOR A 10M 28AWG CABLE
SYMBOL
15
4
t
-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
r
, t
f
V
DD
FIGURE 2. DEVICE CHARACTERIZATION SET UP
20% to 80%
From IN to OUT
= 1.2V, T
100O Twin-Axial
Ω
DD
Cable
. The specified cable input amplitude range is established by characterization and
A
= +25°C, and V
CONDITION
ISL36111
J
IN
) is DJ
= 600mV
Adapter
SMA
Card
pp
+ 14.1 x RJ
P-P
, unless otherwise noted. (Continued)
MIN
RMS
ISL36111 Eval
TYP
500
Board
32
MAX
UNITS
ps
ps
Oscilloscope
October 27, 2010
NOTES
FN6974.1
13