DS32EV400SQ/NOPB National Semiconductor, DS32EV400SQ/NOPB Datasheet - Page 13

• Manufacturer Part Number: DS32EV400SQ/NOPB
• Description: IC EQUALIZER QUAD 3.2GBPS 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS32EV400SQ/NOPB

• Applications: Signal Processing
• Interface: Serial
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 48-LLP
• Mounting Type: Surface Mount
• For Use With: DS32EV400-EVK - KIT EVALUATION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS32EV400SQTR

SIGNAL DETECT
The DS32EV400 features a signal detect circuit on each data
channel. The status of the signal of each channel can be de-
termined by either reading the Signal Detect bit (SDn) in the
SMBus registers (see Table 1) or by the state of each SDn
pin. An output logic high indicates the presence of a signal
that has exceeded the ON threshold value (called SD_ON).
An output logic Low means that the input signal has fallen
below the OFF threshold value (called SD_OFF). These val-
ues are programmed via the SMBus (Table 1). If not pro-
grammed via the SMBus, the thresholds take on the default
values as shown in Table 4. The Signal Detect threshold val-
ues can be changed through the SMBus. All threshold values
specified are DC peak-to-peak differential signals (positive
signal minus negative signal) at the input of the device.
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can
be controlled via the SMBus (see Table 1). The default output
Channel 0:
Channel 1:
Channel 3:
Channel2:
Bit 1
Bit 3
Bit 5
Bit 7
0
0
1
1
TABLE 4. Signal Detect Threshold Values
Channel 0:
Channel 1:
Channel 3:
Channel2:
Bit 0
Bit 2
Bit 4
Bit 6
0
1
0
1
Register 06
40 (Default)
Threshold
SD_OFF
(mV)
30
55
45
Register 05
70 (Default)
Threshold
SD_ON
(mV)
55
90
75
13
level is 620 mVp-p. The following Table presents the output
level values supported:
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving
Standby mode. This can be accomplished by connecting the
Signal detect (SDn) pin to the Enable (ENn) pin for each
channel (See Figure 9). In order for this option to function
properly, the register value for Reg. 07 should be 00'h (default
value). If an input signal swing applied to a data channel is
above the voltage level threshold as shown in Table 4, then
the SDn output pin is asserted High. If the SDn pin is con-
nected to the ENn pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels; thus the
DS32EV400 will automatically enter the ACTIVE state. If the
input signal swing falls below the SD_OFF threshold level,
then the SDn output will be asserted Low, causing the channel
to be placed in the STANDBY state.
All Channels: Bit 3 All Channels: Bit 2
TABLE 5. Output Level Control Settings
0
0
1
1
0
1
0
1
Output Level
620 (Default)
Register 08
(mV
www.national.com
400
540
760
P-P
)