PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet
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PI7C9X7954 PCI Express® Quad UART Datasheet Revision 1.3 September 2009 Telephone: 1-877-PERICOM, (1-877-737-4266) 09-0088 3545 North 1ST Street, San Jose, CA 95134 FAX: 408-435-1100 Internet: http://www.pericom.com ...
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... Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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... September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 Description Preliminary Datasheet Fixed the diagrams Corrected Chapter 4.2 Pin Description (RREF, GPIO[7]) Updated Chapter 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver Setting, 6.2.41 GPIO Control Register ) Revised Chapter 7 ...
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... BASE ADDRESS REGISTER 0 – OFFSET 10h.....................................................................28 6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h.....................................................................28 6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................28 6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................28 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page PI7C9X7954 Datasheet ...
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... CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .............................................42 6.2.64. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h.............43 6.2.65. HEADER LOG REGISTER – OFFSET From 11Ch to 128h .................................................43 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page PI7C9X7954 Datasheet ...
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... LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................62 8. EEPROM INTERFACE .....................................................................................................................63 8.1. AUTO MODE EERPOM ACCESS ...............................................................................................63 8.2. EEPROM MODE AT RESET ........................................................................................................63 8.3. EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................63 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 M .......................................................................................51 ODE Page PI7C9X7954 PCI Express® Quad UART Datasheet ...
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... ELECTRICAL SPECIFICATION.....................................................................................................65 9.1. ABSOLUTE MAXIMUM RATINGS ...........................................................................................65 9.2. DC SPECIFICATIONS..................................................................................................................65 9.3. AC SPECIFICATIONS..................................................................................................................65 10. CLOCK SCHEME ..........................................................................................................................68 11. PACKAGE INFORMATION .........................................................................................................69 12. ORDER INFORMATION ..............................................................................................................70 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page PI7C9X7954 Datasheet ...
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... C S IGURE XTERNAL LOCK OURCE AS THE F 7-1 UART IGURE EGISTER LOCK F 7-2 UART R B IGURE EGISTER LOCK F 11-1 P IGURE ACKAGE OUTLINE DRAWING September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 ................................................................................................24 ETTING .......................................................................................................24 .............................................................................................44 ODE M ....................................................................................51 EMORY ODE .....................................................................................................65 ..............................................................................................65 .................................................................................................65 .......................................................................................................66 ....................................................................................................68 ...................................................................................................10 .................................................................................................. ...........................................................................23 LOCK OURCE ...
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... Multi-port RS-232/ RS-422/ RS-485 Cards Point-of-Sale Systems (PoS) Industrial PC (IPC) Industrial Control Gaming Machines Building Automation Embedded Systems September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 Page PI7C9X7954 PCI Express® Quad UART Datasheet ...
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... CLKINN RREF SR_DI EEPROM SR_CS Interface SR_DO SR_CLK_O Reference XTLO Clock XTLI Figure 3-1 PI7C9X7954 Block Diagram September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART SOUT[3:0] Interrupt SIN[3:0] Interface DCD[3:0] DTR[3:0] RTS[3:0] CTS[3:0] Quad DSR[3:0] UART ...
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... DRIVER_SEL1[2]/DTX[3] 26 RXP 58 DRIVER_SEL1[3]/DEQ[0] 27 VSS 59 DRIVER_SEL2[0] 28 RXN 60 DRIVER_SEL2[1] 29 RREF 61 DRIVER_SEL2[2] 30 VDDA 62 DRIVER_SEL2[3] 31 VSS 63 VDDR 32 VDDA 64 VSS September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PIN NAME 65 DRIVER_SEL3[0] 66 DRIVER_SEL3[1] 67 DRIVER_SEL3[2] 68 DRIVER_SEL3[3] 69 VDDC 70 VSS 71 SOUT[0] 72 RTS[0]/EEPROM_BYPASS 73 DTR[0] 74 SIN[0] 75 CTS[0] 76 DSR[0] 77 RI[0] ...
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... XTLI *52, *51, 50, DRIVER_SEL0 *49 [3:0] September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION O UART Serial Data Outputs: The output pins transmit serial data packets with start and end bits. SOUT[0] and SOUT[1] are output signals with weak internal pull-down resistors. ...
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... RREF 4.2.3. SYSTEM INTERFACE PIN NO. NAME 36 PEREST_L September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION O DRIVER_SEL1: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 1. DRIVER_SEL1 [3:0] are output signals with weak internal pull-down resistors. ...
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... TEST 97, 102, 103, NC 104, 105, 111, 112, 113, 114 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION I/O General-Purpose Bi-Direction Signals / SR_ORG: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. GPIO[ bi-directional signal with a weak internal pull-up resistor, and other GPIO pins are bi-directional signals with weak internal pull-down resistors ...
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... SR_CS 10 SR_DI 9 SR_DO 8 SR_CLK_O September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION O EEPROM Chip Select: SR_CS is an output signal with a weak internal pull-up resistor. I EEPROM Data Input: Serial data input interface to the EEPROM. SR_DI is an input signal with a weak internal pull-up resistor. ...
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... VTT 3, 4, 13, 15, VSS 19, 24, 27, 31, 35, 42, 54, 64, 70, 96, 100, 101, 117, 118 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION P 1.8 V Power Pin: Used as digital core power pins. P 1.8 V Power Pin: Used as analog core power pins. P 3.3 V Power Pin: Used as digital I/O power pins. ...
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... UART’s transmit and receive data FIFOs can be conveniently accessed by reading and writing the registers in the UART configuration space. These registers allow flexible programming capability and versatile device operations of the PI7C9X7954. Each UART is accessed through an 8-byte I/O blocks. The addresses September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page ...
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... I/O Base Address Registers, the transaction is recognized as an I/O Read or Write. 5.2.3. Memory Reads/Writes Similar to the I/O Read/Write, if the address of the transaction packet is within the memory range, a Memory Read/Write occurs. September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page PI7C9X7954 Datasheet ...
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... The data that arrive most recently are written to the bottom of the THR. If the THR is full, and the user attempts to write data to the THR, a data overrun occurs and the data is lost. September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 EFR[4] ...
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... Counter (RFDC) and Transmit FIFO Data Counter (TFDC) registers to determine the number of items in each FIFO. RHR WP RP DATA125 DATA126 DATA127 Figure 5-1 Transmit and Receive FIFOs September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI EXPRESS MASTER UART COMMON MODE ADDRESS LSR THR DATA0 DATA0 LSR0 ...
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... The UART deasserts RTS# to signal the remote transmitter that the local receive FIFO reaches the programmed upper trigger level. When the local receive FIFO falls below the programmed lower trigger level, the RTS# is reasserted. The automatic out-of-band flow control is enabled by EFR[7:6]. September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page ...
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... This feature provides the users a way to perform system diagnostics by allowing the UART to receive the same data it is sending. Figure 5-2 Internal Loopback in PI7C9X7954 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART VCC ...
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... When a crystal oscillator is used, the XTLI is the input and XTLO is the output, and the crystal should be connected in parallel with two capacitors. Figure 5-3 Crystal Oscillator as the Clock Source VCC GND Figure 5-4 External Clock Source as the Clock Source September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 XTLI R XTLO 14.7456 MHz C1 ...
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... Power Management The PI7C9X7954 supports the D0, D1, D2 and D3 power states. The device is compliant with PCI Power Management Specification Revision 1.2. September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 ency escaler 1 SampleCloc (SCR = ‘0h’ to ‘Ch’) ...
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... Vendor Define Register(28h) ACK Latency Timer Power Management Control Parameter EEPROM Data PCI Express Capability Register Device Status Link Status September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 DEFINITION Hardware Initialization Read Only Write Only Read / Write Read / Write 1 to Clear ...
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... Enable Memory Write And 4 Invalidate Enable VGA Palette Snoop 5 Enable Parity Error 6 Response Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 23 – – 8 Reserved 23 – – 8 PCI Express Extended Capability ID = 001h Correctable Error Status Register Correctable Error Mask Register Header Log Register ...
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... BIT FUNCTION 7:0 Revision 6.2.6. CLASS CODE REGISTER – OFFSET 08h September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Reset to 0b. RO Does not apply to PCI Express. Must be hardwired to 0b. This bit, when set, enables reporting of Non-fatal and Fatal errors detected by the device to the Root Complex ...
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... Sub Vendor ID 6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch BIT FUNCTION 31:16 Sub System ID September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO Read as 02h to indicate no programming interfaces have been defined for PCI-to-PCI bridges RO Read as 00h to indicate device is PCI-to-PCI bridge ...
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... AUX Current D1 Power State 25 Support D2 Power State 26 Support September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION This optional register points to a linked list of new capabilities implemented by the device. This default value may be changed by RO auto-loading from EEPROM. The default value is 80h. ...
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... MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch BIT FUNCTION Enhanced 7:0 Capability ID September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Read as 01000b to indicate the I/O bridge supports the forwarding of RO PME# message in all power states. The default value may be changed by auto-loading from EEPROM ...
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... Next Item Pointer 6.2.30. VPD REGISTER – OFFSET 9Ch BIT FUNCTION 16 VPD Start 17 VPD Operation September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION The pointer points to the Vendor Specific capability register (9Ch). RO Reset to 9Ch. TYPE DESCRIPTION RO Reset to 00b. ...
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... Reserved 6.2.37. REPLAY TIME-OUT COUNTER – OFFSET B0h BIT FUNCTION 11:0 User Replay Timer September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Contains DWORD address that is used to generate read or write cycle to the VPD table stored in EEPROM. RW Reset to 00000b. ...
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... Transmitter Driver Enable 27:12 Reserved UART 3 31:28 Transmitter Driver Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION When asserted, the user-defined replay time-out value would be employed. The default value may be changed by auto-loading from RW EEPROM. Reset to 0b. RO Reset to 000b. ...
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... Termination Adjustment 31:14 Reserved 6.2.45. GPIO CONTROL REGISTER – OFFSET D8h BIT FUNCTION 7:0 GPIO Input September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION The default value may be changed by auto-loading from EEPROM. RW Reset to 000001b. RO Reset to 0000000h. TYPE DESCRIPTION Used for test purpose only ...
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... Slot Implemented Interrupt Message 29:25 Number 31:30 Reserved September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION These 8 bits determine whether the GPIO pins are input or output pins. Bit[x+8] corresponds to GPIO[x], where x the bit is RW set to “0”, the corresponding GPIO pin is an input pin. If the bit is set to “ ...
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... Non-Fatal Error 1 Reporting Enable Fatal Error 2 Reporting Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Indicates the maximum payload size that the I/O bridge can support for TLPs. The I/O bridge supports 128 bytes max payload size. RO Reset to000b. ...
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... Detected Transactions 21 Pending 31:22 Reserved 6.2.53. LINK CAPABILITIES REGISTER – OFFSET ECh BIT FUNCTION September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION 0b: Disable Unsupported Request Reporting. 1b: Enable Unsupported Request Reporting. RW Reset to 0b not implemented. RO Reset to 0b. This field sets maximum TLP payload size for the device. ...
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... Extended Synch 15:8 RsvdP 6.2.55. LINK STATUS REGISTER – OFFSET F0h BIT FUNCTION September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Indicates the Maximum Link Speed of the given PCIe Link. RO Defined encodings are: 0001b, which indicates 2.5 Gb/s Link Reset to 1h ...
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... Error Status 11:5 Reserved Poisoned TLP 12 Status September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Indicates the negotiated Link Speed of the given PCIe Link. RO Defined encodings are: 0001b, which indicates 2.5 Gb/s Link Reset to 1h. Indicates the negotiated width of the given PCIe Link, RO Reset to 000001b ...
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... Timeout Mask Completer Abort 15 Mask Unexpected 16 Completion Mask September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION When set, indicates that the Flow Control Protocol Error event has occurred. RW1CS Reset to 0b. When set, indicates that the Completion Timeout event has occurred. ...
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... Severity Receiver Overflow 17 Severity Malformed TLP 18 Severity September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION When set, the Receiver Overflow event is not logged in the Header Log register and not issued as an Error Message to RC either. RWS Reset to 0b. When set, an event of Malformed TLP has been received is not ...
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... Bad TLP Mask 7 Bad DLLP Mask REPLAY_NUM 8 Rollover Mask 11:9 Reserved Replay Timer 12 Timeout Mask 31:13 Reserved September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION 0b: Non-Fatal. 1b: Fatal. RWS Reset to 0b. 0b: Non-Fatal. 1b: Fatal. RWS Reset to 0b. RO Reset to 000h . TYPE DESCRIPTION When set, the Receiver Error event is detected ...
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... DWORD th 15:12 4 DWORD September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION It indicates the bit position of the first error reported in the Uncorrectable Error Status register. ROS Reset to 00000b. When set, it indicates the I/O bridge has the capability to generate ECRC. ...
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... UART UART I/O Base Address UART0 BAR0 + 000h UART1 BAR0 + 008h UART2 BAR0 + 010h UART3 BAR0 + 038h September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 UART I/O Base Address 000h UART0 Registers 008h UART1 Registers 010h UART2 Registers 038h UART3 Registers ...
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... Rx Status Interrupt 3 Modem Status Interrupt 4 Xoff/Special character interrupt 5 RTS Interrupt September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 Register Name Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register Line Control Register Modem Control Register ...
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... Tx FIFO Flush 3 Reserved 5:4 Tx Trigger Level 7:6 Rx Trigger Level 7.1.6. LINE CONTROL REGISTER – OFFSET 03h BIT FUNCTION September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RW 0b: Disable CTS/DSR interrupt 1b: Enable CTS/DSR interrupt Reset to 0b. RW TYPE DESCRIPTION RO 0b: An interrupt is pending 1b: No interrupt pending Reset to C1h ...
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... DTR Pin Control 1 RTS Pin Control 2 Output 1 3 Output 2 4 Internal Loopback Mode September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RW 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length Reset to 11b. RW ...
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... Rx Frame Error 4 Rx Break Error 5 Tx Empty 6 Tx Complete September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RW Autoflow Control Enable. When the AFE is enabled, autoflow control is enabled. When it is disabled, the diagnostic mode is enabled. In the diagnostic mode, transmitted data is immediately received. When AFE is set to “ ...
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... Force Transmission 1 Auto DSR and DTR Flow Control 2 Reserved 3 Reserved 4 Reserved September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO 0b FIFO error 1b: Rx FIFO error Reset to 0b. TYPE DESCRIPTION RO 0b: No change in CTS input. 1b: Indicates the CTS input has changed state. ...
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... Divisor High 7.1.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[ BIT FUNCTION 3:0 Sample Clock 7:4 Reserve September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RW 1b: Enables 950 mode 0b: Non-950 mode Reset to 0b. RW 1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter 0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter Reset to 0b ...
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... UART I/O Base Address UART0 BAR1 + 0000h UART1 BAR1 + 0200h UART2 BAR1 + 0400h UART3 BAR1 + 0E00h September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART 0000h UART0 Registers 0200h UART1 Registers 0400h UART2 Registers 0E00h UART3 Registers ...
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... UART Memory Base Address + 180h ~1FFh 7.2.1. RECEIVE HOLDING REGISTER – OFFSET 00h BIT FUNCTION 7:0 Rx Holding September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 Register Name Mnemonic Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register ...
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... September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION WO When data are written to the Transmit Holding Register (THR), they are written to the bottom of the transmitter’s associated FIFOs, which holds a queue of data to be transmitted by the transmitter. Data written to the THR when the FIFOs are full are lost. The Line Status Register (LSR) indicates the full or empty status of the FIFOs ...
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... Rx FIFO Flush 2 Tx FIFO Flush 3 Reserved 5:4 Tx Trigger Level 7:6 Rx Trigger Level 7.2.6. LINE CONTROL REGISTER – OFFSET 03h BIT FUNCTION 1:0 Data Length 2 Stop-Bit Length 5:3 Parity Type September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION WO 0b: Disable the FIFO mode 1b: Enable the FIFO mode Reset to 0b ...
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... Internal Loopback Mode 5 AFE 6 Reserved 7 Enhanced Transmission September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RW 0b: No transmit break condition 1b: Force the transmitter output to a space for alerting the remote receiver of a line break condition. Reset to 0b. RW 0b: Data registers are selected 1b: Divisor latch registers are selected Reset to 0b ...
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... BIT FUNCTION 0 Delta CTS 1 Delta DSR 2 Delta RI 3 Delta DCD 4 CTS September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO 0b: No data in the receive FIFO 1b: Data in the receive FIFO Reset to 0b. RO 0b: No overrun error 1b: Overrun error Reset to 0b. RO 0b: No parity error 1b: Parity error Reset to 0b ...
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... ENHANCED FUNCTION REGISTER – OFFSET 0Ah BIT FUNCTION 1:0 In-Band Receive Flow Control Mode September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO 0b: The DSR input state is the logic 0 1b: The DSR input state is the logic 1 Reset to 0b. ...
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... Flow Control Enable 7 Automatic CTS Flow Control Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION character(s). When this occurs, the UART will disable transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed XON character(s) ...
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... XOFF2 7.2.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh BIT FUNCTION 0 Transmitter Terminate Condition 1 Remote TX Disable 2 Xon/Xoff Detect September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION Reset to 0b. TYPE DESCRIPTION RW Xon character 1. Reset to 00h. TYPE DESCRIPTION RW Xon character 2. Reset to 00h. ...
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... RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[ The function of this register is selected by the Special Function Register (Offset 07h) bit 6. When SFR[6] is set to ‘1’, this register functions as the Receive FIFO Data Counter. Otherwise, it functions as the Line September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION ...
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... GLOBAL LINE STATUS REGISTER – OFFSET 17h BIT FUNCTION 0 RX Data Available 1 RX FIFO Overrun September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO The Receive FIFO Data Counter indicates the amount of data in the Receive FIFO. Reset to 00h. TYPE ...
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... FUNCTION 7:0 Transmit FIFO Data 7.2.31. LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh BIT FUNCTION 7:0 Line Status FIFO September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 TYPE DESCRIPTION RO 0b: No parity error 1b: Parity error Reset to 0b. RO 0b: No framing error 1b: Framing error Reset to 0b ...
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... Offset B0h bit [31:16] 10h Bit[1:0] - Offset ECh bit[11:10] Bit[4:2] - Offset ECh bit[14:12] Bit[7:5] - Offset ECh bit[17:15] 12h Offset B4h bit[15:0] September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART DEFAULT DESCRIPTION Value A868h Check Code 12D8h ...
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... Bit[13:0] - Offset C8h bit[13:0] 1Ah Bit[0] - Offset C4h bit[15] Bit[15:8] - Offset 34h bit[7:0] 1Ch [7:0] - Offset 08h bit[7:0] 40h September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART DEFAULT DESCRIPTION Value 0000h UART Transmitter Drive Enable: RS232/422/485-2W/485-4W Selection for UART 4 ...
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... TX-CM-AC V Transmit common-mode voltage in L0s TX-CM-HiZ (TX) & De-emphasized differential output TX-DE-RATIO voltage V Electric Idle differential peak voltage TX-IDLE-DIFFp September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Typ. Max. 1.8v 2.0v 1.8v 2.0v 1.8v 2.0v VDDC 2.0v 3 ...
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... Maximum time between jitter RX-EYE-MEDIAN-to-MAX-JITTER median and max deviation from median Timing Parameters LRLAT-10 Receiver data latency for n=10 LRLAT-20 Receiver data latency for n=20 September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Min Typical V TX-DIFFp ...
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... Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Min Typical ...
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... Duty cycle of input clock Rise/Fall time of input clock Differential input voltage swing SW a. RCUI (Reference Clock Unit Interval) refers to the reference clock period September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Min Typical - 100 (zero-to-peak) 0.4 ...
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... PACKAGE INFORMATION The package of PI7C9X7954 is a 14mm x 14mm LQFP (128 Pin) package. The following are the package information and mechanical dimension: Figure 11-1 Package outline drawing September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 PCI Express® Quad UART Page PI7C9X7954 ...
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... Order Information Part Number Temperature Range o □ - PI7C9X7954 FDE (Industrial Temperature 9X7954 FD E September 2009 – Revision 1.3 Pericom Semiconductor 09-0088 Package o C 128-pin LQFP 14mm x 14mm Blank=Standard E=Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family PI=Pericom ...