ISL54101ACQZ Intersil, ISL54101ACQZ Datasheet
ISL54101ACQZ
Specifications of ISL54101ACQZ
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ISL54101ACQZ Summary of contents
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... All other trademarks mentioned are the property of their respective owners. FN6725 software-controlled operation 4X2 TMDS TX TMDS OUT 4X2 TMDS TX TMDS OUT 4X2 TMDS TX TMDS OUT Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved ...
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... CHANNELS ISL54100ACQZ ISL54101ACQZ ISL54102ACQZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Thermal Resistance (Typical, Note 1) +0.3V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 D Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage 3.3V, pixel rate = 165MHz COMMENT ...
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Electrical Specifications Specifications apply for V TMDS output load = 50Ω, TMDS output termination voltage V SYMBOL PARAMETER DIGITAL OUTPUT CHARACTERISTICS V Output HIGH Voltage 8mA Output LOW Voltage -8mA OL O POWER ...
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ISL54100A Pin Configuration 1 ADDR2 RX2-_B 5 RX2+ GND RXC-_A 10 RXC+ RXC-_B 13 RXC+ GND GND 18 GND 19 ...
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ISL54101A Pin Configuration 1 ADDR2 GND RXC-_A 10 RXC+ GND GND 18 GND 19 ...
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ISL54102A Pin Configuration 1 ADDR2 RX2-_B 5 RX2+ GND RXC-_A 10 RXC+ RXC-_B 13 RXC+ GND GND 18 GND 19 ...
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Pin Descriptions SYMBOL RX0-_A, RX0+_A, RX1-_A, RX1+_A, TMDS Inputs. Incoming TMDS data signals for Channel A. RX2-_A, RX2+_A RX0-_B, RX0+_B, RX1-_B, RX1+_B, TMDS Inputs. Incoming TMDS data signals for Channel B (ISL54100A and ISL54102A only). RX2-_B, RX2+_B RX0-_C, RX0+_C, RX1-_C, ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 Channel Activity Detect (read only) 0x02 Channel Selection (0x0C) 9 ISL54100A, ISL54101A, ISL54102A BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon second revision, etc. ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x03 Input Control (0x12) Recommended default: 0x62 10 ISL54100A, ISL54101A, ISL54102A BIT(S) FUNCTION NAME 0 Tri-state Unselected 0: Normal Operation Clock Inputs 1: Termination of unselected TMDS clock inputs is tri-stated to save ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x04 Termination Control (0x00) 0x05 Output Options (0x00) 0x06 Data Output Drive (0x00) 11 ISL54100A, ISL54101A, ISL54102A BIT(S) FUNCTION NAME 0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x07 Equalization 1 (0xCC) 0x08 Equalization 2 (0xCC) 0x09 Test Pattern Generator (0x00) 0x0A PRBS7 Error Counter Link 0 (read only) 0x0B PRBS7 Error Counter Link 1 (read only) 0x0C PRBS7 Error Counter ...
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Application Information The ISL54100A, ISL54101A, and ISL54102A are TMDS regenerators, locking to the incoming DVI or HDMI signal with triple Clock Data Recovery units (CDRs) and a Phase Locked Loop (PLL). The PLL generates a low jitter pixel clock from ...
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Tx Pre-emphasis The transmit pre-emphasis function sinks additional current during the first bit after every transition, increasing the slew rate for a given capacitance, and helping to maintain the slew rate when using longer/higher capacitance cables. Pre-emphasis is controlled by ...
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ISL5410xAs that can be put in series (although statistically unlikely that all the skews would line worst-case configuration). Typical Performance Setup A (Figure 4) was used to capture the ...
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FIGURE 9. ISL54100 EYE DIAGRAM AFTER 15m CABLE Tx Loading Considerations When the ISL5410xA is powered-up and its Tx outputs are disabled, via either the PD (power-down) pin, the power-down register bit (register 0x02[5]), or the tri-state outputs bits (register ...
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Minimize capacitance on all TMDS lines. The lower the capacitance, the sharper the rise and fall times. • Maintain a constant, solid ground (or power) plane under the 3 high speed TMDS signals. Do not route the signals over ...
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The ISL5410xA has a 7-bit address on the serial bus, determined by the ADDR0-ADDR6 bits. This allows up to 128 ISL5410xAs to be independently controlled by the same serial bus. The bus is nominally inactive, with SDA and SCL high. ...
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ISL54100A, ISL54101A, ISL54102A START Command ISL5410xA Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 (Repeat if desired) STOP Command S T Serial Bus Register A Signals from Address Address R the ...
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ISL54100A, ISL54101A, ISL54102A START Command ISL5410xA Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 START Command ISL5410xA Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 (Repeat if desired) STOP Command S T ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...