PCA9518AD,118 NXP Semiconductors, PCA9518AD,118 Datasheet

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PCA9518AD,118

Manufacturer Part Number
PCA9518AD,118
Description
IC I2C BUS HUB 5-CH 20SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9518AD,118

Package / Case
20-SOIC (7.5mm Width)
Applications
CMOS Bus Controller
Interface
I²C
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Logic Family
PCA9518A
Operating Supply Voltage
2.3 V to 3.6 V
Power Dissipation
300 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C Bus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935284253118
PCA9518AD-T
PCA9518AD-T
1. General description
1.
Only four ports per device are available if individual Enable is required.
The PCA9518A is a CMOS integrated circuit intended for application in I
SMBus systems.
While retaining all the operating modes and features of the I
extension of the I
enabling virtually an unlimited number of buses of 400 pF.
The I
Using the PCA9518A enables the system designer to divide the bus into an unlimited
number of segments off of a hub where any segment to segment transition sees only one
repeater delay and is multiple master capable on each segment.
Using multiple PCA9518A parts, any width hub (in multiples of five)
using the expansion pins.
The PCA9518A is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also
improves partial power-down performance, keeping I
state when V
A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another
PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518
devices into any size cluster thanks to the EXPxxxn pins that allow the I
be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since
there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid
lock-up conditions between the input and the output of individual repeaters in the cluster.
A ‘regular LOW’ applied at the input of any of the PCA9518 devices will then be
propagated as a ‘buffered LOW’ with a slightly higher LOW value to all enabled outputs in
the PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or
separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second
PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and
will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and
PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 either,
but can be used in series with themselves since they use shifting instead of static offsets
to avoid lock-up conditions. This note is applicable to the ‘A’ versions of these devices
also.
PCA9518A
Expandable 5-channel I
Rev. 03 — 3 December 2008
2
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
DD
is below 2.0 V.
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
2
C-bus hub
2
C-bus I/O pins in high-impedance
2
C-bus system, it permits
1
Product data sheet
can be implemented
2
2
C-bus signals to
C-bus and

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PCA9518AD,118 Summary of contents

Page 1

PCA9518A Expandable 5-channel I Rev. 03 — 3 December 2008 1. General description The PCA9518A is a CMOS integrated circuit intended for application in I SMBus systems. While retaining all the operating modes and features of the I extension of ...

Page 2

... NXP Semiconductors 2. Features I Expandable 5 channel, bidirectional buffer C-bus and SMBus compatible I Active HIGH individual repeater enable inputs I Open-drain input/outputs I Lock-up free operation I Supports arbitration and clock stretching across the repeater I Accommodates Standard-mode and Fast-mode I I Powered-off high-impedance I I Operating supply voltage range of 2 3.6 V ...

Page 3

... NXP Semiconductors 4. Block diagram EXPSCL1 EXPSCL2 SCL0 SCL1 SCL2 EXPSDA1 EXPSDA2 SDA0 SDA1 SDA2 EN1 EN2 Fig 1. Block diagram of PCA9518A A more detailed view of Fig 2. The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven LOW ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 V Fig 3. 5.2 Pin description Table 2. Symbol EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 V SS EN2 SCL3 SDA3 EN3 SCL4 SDA4 EN4 EXPSDA1 EXPSDA2 V DD ...

Page 5

... NXP Semiconductors 6. Functional description The PCA9518A CMOS integrated circuit is a five-way hub repeater, which enables 2 I C-bus and similar bus systems to be expanded in increments of five with only one repeater delay and no functional degradation of system performance. The PCA9518A CMOS integrated circuit contains five multi-directional, open-drain buffers specifi ...

Page 6

... NXP Semiconductors Standard-mode devices and multiple masters are possible. Please see application note AN255, I resistors. 7. Application design-in information A typical application is shown 3 100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master bus and slave 1, slave 2 and slave 6 can run at 400 kHz. ...

Page 7

... NXP Semiconductors 5 V SDA SDA1 SCL SCL1 SUBSYSTEM 5 100 kHz 3.3 V SDA SDA2 SCL SCL2 SUBSYSTEM 6 400 kHz 3 PCA9518A DEVICE 2 SDA3 SCL3 3 disabled; not connected SDA4 SCL4 Only two of the five channels on the PCA9518A Device 2 are being used. EN3 and EN4 are connected to V ...

Page 8

... NXP Semiconductors the acknowledge and then returns to the PCA9518A level creating a foot before it completes the LOW-to-HIGH transition. SDA lines other than the one with the master and the one with the slave have a uniform LOW level driven by the PCA9518A repeater. The other four waveforms are the expansion bus signals and are included primarily for timing reference points ...

Page 9

... NXP Semiconductors V SCL of master Bus 0 SDA of master t PHL1 EXPSDA1 t PHL2 EXPSDA2 expansion bus EXPSCL1 EXPSCL2 SCL of slave Bus 1 SDA of slave t PHL Bus n with n > 1 Fig 6. Bus waveforms It is important to note that any arbitration or clock stretching events on Bus 1 require that the the Section 9 “ ...

Page 10

... NXP Semiconductors 8. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I2C-bus tot T stg T amb [1] Voltages with respect to pin V PCA9518A_3 Product data sheet Limiting values Parameter supply voltage 2 I C-bus voltage input current total power dissipation ...

Page 11

... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics [ 3 3 Symbol Parameter Supplies V supply voltage DD I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply current V CCLc Input SCL; input/output SDA V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage ...

Page 12

... NXP Semiconductors Table 5. Static characteristics [ 2 2 Symbol Parameter Supplies V supply voltage DD I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply current V CCLc Input SCL; input/output SDA V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage ...

Page 13

... NXP Semiconductors 10. Dynamic characteristics Table 6. Dynamic characteristics [ 3 3 Symbol Parameter t HIGH to LOW propagation delay PHL t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay 1 PHL1 t LOW to HIGH propagation delay 1 PLH1 t LOW to HIGH propagation delay 2 PLH2 t HIGH to LOW output transition time THL ...

Page 14

... NXP Semiconductors Table 7. Dynamic characteristics [ 2 2 Symbol Parameter t HIGH to LOW propagation delay PHL t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay 1 PHL1 t LOW to HIGH propagation delay 1 PLH1 t LOW to HIGH propagation delay 2 PLH2 t HIGH to LOW output transition time THL t LOW to HIGH output transition time ...

Page 15

... NXP Semiconductors 11. Test information Fig 8. PCA9518A_3 Product data sheet PULSE GENERATOR load resistor; 1.1 k for I C-bus, and 500 load capacitance includes jig and probe capacitance; 100 pF for I L EXPxxxn termination resistance should be equal Test circuit for open-drain outputs Rev. 03 — 3 December 2008 ...

Page 16

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 19

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 20

... NXP Semiconductors Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM I C-bus MM RC SMBus PCA9518A_3 Product data sheet ...

Page 21

... NXP Semiconductors 15. Revision history Table 11. Revision history Document ID Release date PCA9518A_3 20081203 • Modifications: Section 6.1 • Figure 5 “Typical application: multiple expandable 5-channel I below drawing. PCA9518A_2 20081001 PCA9518A_1 20070606 PCA9518A_3 Product data sheet Data sheet status Product data sheet rd “Enable”: added new 3 ...

Page 22

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Enable 6.2 Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.3 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Application design-in information . . . . . . . . . . 6 8 Limiting values Static characteristics Dynamic characteristics ...

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