MCZ33904A5EK Freescale Semiconductor, MCZ33904A5EK Datasheet

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MCZ33904A5EK

Manufacturer Part Number
MCZ33904A5EK
Description
IC SYSTEM BASIS CHIP 32-SOIC
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCZ33904A5EK

Applications
System Basis Chip
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 27 V
Package / Case
32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Freescale Semiconductor
Advance Information
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
SBC Gen2 with CAN High Speed
and LIN Interface
Chips, which combines several features and enhances present module
designs. The device works as an advanced power management unit for
the MCU, additional integrated circuits such as sensors, and CAN
transceivers. It has a built-in enhanced high speed CAN interface
(ISO11898-2 and -5), with local and bus failure diagnostics, protection,
and fail safe operation mode. The SBC may include one or two LIN 2.1
interfaces with LIN output pin switches. It includes up to four wake-up
input pins than can also be configured as output drivers for flexibility.
current consumption. In addition, the device is part of a family concept
where pin compatibility, among the various devices with and without
LIN interfaces, add versatility to module design.
state machine and concept solution.
Features
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
• Voltage, current, and temperature protection
• Extremely low quiescent current in low power modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple under-voltage detections to address various MCU
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs,
• MUX output pin for device internal analog signal monitoring and
• Advanced SPI, MCU, ECU power supply, and critical pins
• Multiple wake-up sources in low power modes: CAN or LIN bus, I/O
• ISO11898-5 high speed CAN interface compatibility for baud rates of
• Pb-free packaging designated by suffix code EK
The 33903/4/5 is the second generation family of System Basis
This device implements multiple Low Power modes, with very low-
The 33903/4/5 also implements an innovative and advanced fail-safe
possibility of usage external PNP to extend current capability and
share power dissipation
specifications and system operation modes (i.e. cranking)
with over-current detection and under-voltage protection
power supply monitoring
diagnostics and monitoring.
transition, automatic timer, SPI message, and V
detection.
40 kb/s to 1.0 Mb/s
DD
over-current
See
EK SUFFIX (PB-FREE)
Device Variations on page 2
98ASA10556D
32-PIN SOIC
SYSTEM BASIS CHIP
ORDERING INFORMATION
Document Number: MC33903_4_5
33903/4/5
33903/
EK SUFFIX (PB-FREE)
Rev. 5.0, 12/2010
98ASA10506D
54-PIN SOIC

Related parts for MCZ33904A5EK

MCZ33904A5EK Summary of contents

Page 1

... Mb/s • Pb-free packaging designated by suffix code EK * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. Document Number: MC33903_4_5 SYSTEM BASIS CHIP EK SUFFIX (PB-FREE) ...

Page 2

... MCZ33905D5EK/R2 5.0 V *MCZ33905BD5EK/R2 MC33905S (Single LIN) MCZ33905S3EK/R2 3.3 V *MCZ33905BS3EK/R2 MCZ33905S5EK/R2 5.0 V *MCZ33905BS5EK/R2 MC33904 MCZ33904A3EK/R2 3.3 V *MCZ33904B3EK/R2 MCZ33904A5EK/R2 5.0 V *MCZ33904B5EK/R2 MC33903 *MCZ33903B3EK/R2 (1) 3.3 V *MCZ33903B5EK/R2 (1) 5.0 V Notes 1. V does not allow usage of an external PNP on the 33903. Output current limited to 100 mA “ ...

Page 3

... LIN Block ................................................................................................................................................. 55 LIN Interface Description ...................................................................................................................... 55 LIN Operational Modes ......................................................................................................................... 55 Serial Peripheral Interface ....................................................................................................................... 57 High Level Overview ............................................................................................................................. 57 Detail Operation .................................................................................................................................... 58 Detail of Control Bits And Register Mapping ........................................................................................ 61 Flags and Device Status ....................................................................................................................... 79 Typical Applications ................................................................................................................................ 86 Packaging ............................................................................................................................................... 91 Analog Integrated Circuit Device Data Freescale Semiconductor TABLE OF CONTENTS TABLE OF CONTENTS 33903/4/5 3 ...

Page 4

... MOSI VSENSE SCLK MISO I/O-0 CS MUX-OUT I/O-1 5V-CAN CANH TXD SPLIT RXD CANL TXD-L LIN-T RXD-L LIN I/O-3 * = Option V DD SPI MCU A/D * = Option V DD SPI MCU A/D Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 5

... V BAT D1 V BAT CAN Bus Figure 3. 33904 Simplified Application Diagram V BAT D1 CAN Bus Figure 4. 33903 Simplified Application Diagram Analog Integrated Circuit Device Data Freescale Semiconductor 33904 (5.0 V/3 Q1* VBAUX VCAUX VSUP1 VAUX VE VB VDD VSUP2 SAFE RST DBG INT GND MOSI ...

Page 6

... Enhanced High Speed CAN Physical Interface V S2-INT LIN 2.1 Interface - #1 V S2-INT LIN 2.1 Interface - #2 Figure 5. 33905D Internal Block Diagram VE VB VDD RST INT MOSI SCLK SPI MISO CS MUX-OUT 5 V-CAN TXD RXD TXD-L1 RXD-L1 TXD-L2 RXD-L2 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 7

... VSUP2 SAFE DBG GND VSENSE I/O-0 I/O-1 I/O-3 CANH SPLIT CANL LIN-T LIN Analog Integrated Circuit Device Data Freescale Semiconductor VCAUX VBAUX VAUX VSUP1 5 V Auxiliary V Regulator Regulator DD V S2-INT Fail Safe Power Management State Machine Oscillator Analog Monitoring Signals Condition & Analog MUX ...

Page 8

... Enhanced High Speed CAN Physical Interface Figure 8. 33903 Internal Block Diagram VE VB VDD RST INT MOSI SCLK SPI MISO CS MUX-OUT 5 V-CAN TxD RXD VDD RST INT MOSI SCLK SPI MISO CS 5 V-CAN TxD RXD Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 9

... SAFE 5 5V-CAN 6 CANH 7 CANL 8 GROUND GND CAN 9 SPLIT 10 V-BAUX 11 V-CAUX 12 V-AUX 13 MUX-OUT 14 I/O-0 15 DBG 16 GND - LEAD FRAME 32 pins exposed package Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS VSUP1 50 VE VSUP2 RXD 49 I/O-3 LIN-T 48 TXD 47 SAFE VDD 5V-CAN 46 MISO CANH 45 ...

Page 10

... A capacitor must be connected to this pin. CAN high output. CAN low output. Power GND of the embedded CAN interface Output pin for connection to the middle point of the split CAN termination Output pin for external path PNP transistor base Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 11

... TXD N/A 33905D RXD-L1 33905S RXD N/A VSENSE N Analog Integrated Circuit Device Data Freescale Semiconductor Functional Pin Description Pin Function Formal Name VCAUX Output VCOLLECTOR Auxiliary VAUX Output VOUT Auxiliary Output Multiplex Output I/O-0 Input/Output Input/Output 0 DBG Input Debug TXD-L2 Input ...

Page 12

... CAN bus transmit data input. Internal pull-up to VDD CAN bus receive data output Connection to the external PNP path transistor. This is an intermediate current supply source for the V regulator DD Base output pin for connection to the external PNP pass transistor Ground Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 13

... DC Voltage at RST DC Voltage at MOSI, MSIO, SCLK and CS DC Voltage at MUX-OUT DC Voltage at DBG Continuous current on CANH and CANL DC voltage at VDD, 5V-CAN, VAUX, VCAUX DC voltage at VBASE, VE, VBAUX DC voltage at VSENSE Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Symbol V V SUP1/2TR V V ...

Page 14

... Value Unit V ±8000 ±2000 ±750 ±500 ±15000 ±15000 ±15000 ±9000 ±12000 ±7000 150 °C -40 to 125 °C -55 to 165 °C (5) 50 °C/W °C Note 4 = 1500 Ω), the Charge Device Model ZAP Bottom view Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 15

... Device functional, some parameters could be out of spec. V reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational Run mode, CAN interface in Sleep mode, 5 V-CAN and V Analog Integrated Circuit Device Data Freescale Semiconductor ≤ °C ≤ T ≤ 125 °C, unless otherwise noted. Typical values SUP ° ...

Page 16

... V 4.75 5.0 5.25 3.135 3.3 3.465 - - 1.0 3.0 - 0.1 1 200 400 mV 5 0 threshold (4.0 V result, the dropout SUP Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 17

... Current limitation will report into a flag. 12. Generate a reset or an INT. SPI programmable 13. Generate a reset 14. In Run mode Analog Integrated Circuit Device Data Freescale Semiconductor ≤ °C ≤ T ≤ 125 °C, unless otherwise noted. Typical values SUP °C under nominal conditions, unless otherwise noted. A Symbol ...

Page 18

... V - 0.5 1 0.5 1 0.4 1 0.4 1.4 V μA - 0.1 3.0 1.4 2.0 2.9 V 2.1 3.0 3.8 V 0.2 1.0 1.4 V μA -5.0 1.0 5.0 - 100 - kΩ V 8.1 8.6 9 9.1 0.1 0.25 0.5 - 125 - kΩ Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 19

... V DD Notes 16. When C is higher than CMUX, a serial resistor must be inserted Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS ≤ °C ≤ T ≤ 125 °C, unless otherwise noted. Typical values SUP °C under nominal conditions, unless otherwise noted. ...

Page 20

... HIGH 0 IOUT HIGH 2.5 IOUT LOW 2.5 Analog Integrated Circuit Device Data Typ Max Unit - 0.2 1.0 V Ω 4.3 V μ 100 6 1 μA - 2.0 μA 370 500 - µA -650 -200 -250 -175 5.0 9.0 mA 5.0 9.0 Freescale Semiconductor ...

Page 21

... VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via resistor instances are guaranteed by design and device characterization. 18. Guaranteed by design and device characterization. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ °C ≤ T ≤ 125 °C, unless otherwise noted. Typical values SUP °C under nominal conditions, unless otherwise noted. ...

Page 22

... V 7 SUP1 SUP SUP 8 7 200 -1 -1 100 - - 0.4 0 0.475 0.5 0.525 - - 0.175 - 5.3 5 140 160 180 - 10 - Analog Integrated Circuit Device Data Freescale Semiconductor Unit V µ µA mA µA V SUP V SUP V SUP V SUP V kΩ °C °C ...

Page 23

... INT pulse duration (refer to SPI for selection. Guaranteed by design) short (25 to 125 °C) short (-40 °C) long (25 to 125 °C) long (-40 °C) Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS ≤ °C ≤ T ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical SUP A 25 ° ...

Page 24

... Typ Max Unit μ - 300 600 1000 µs 300 600 1000 µs 60 120 210 110 140 ns 100 120 200 150 140 200 - - 200 - ns - 300 - - 300 - μs 0.5 2.0 5.0 300 - - ns μ 120 max. CAN-WU1 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 25

... OFF mode DD From Low Power V ON mode DD TXD Permanent Dominant State Delay (guaranteed by design) Analog Integrated Circuit Device Data Freescale Semiconductor ≤ °C ≤ T ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical SUP A 25 °C under nominal conditions, unless otherwise noted ...

Page 26

... Figure 13. CAN Signal Propagation Delays TXD to CAN and CAN to RXD 33903/4/5 26 TIMING DIAGRAMS PCLK t WCLKL t SIH Di 0 Don’ Figure 11. SPI Timings t LRD 0 LDR 0 TRD 0 TDR 0 RRD 0 LAG Di n Don’ SODIS 0 RDR 0 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 27

... SUP TH REC(MIN) 28. SUP DOM(MIN) RXD Output of receiving Node 1 t REC_PDF(1) RXD Output of receiving Node 2 Figure 15. LIN Timing Measurements for Normal Slew Rate Analog Integrated Circuit Device Data Freescale Semiconductor VSUP 5 V_CAN 100 nF CANH TXD CANL RXD SPLIT GND t BIT t BUS_REC (MAX) ...

Page 28

... Figure 17. LIN Wake-up Low Power V 33903/4 BIT t BUS_REC (MAX BUS_DOM (MIN) BUS_REC t REC_PDR(1) t REC_PDR(2) V 0.4 V SUP Dominant level T PROPWL OFF Mode Timing DD (MIN) Thresholds of receiving node 1 Thresholds of receiving node 2 (MAX) t REC_PDF(2) BUSWU 3V T WAKE Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 29

... V LIN_REC LIN IRQ Figure 18. LIN Wake-up Low Power V Analog Integrated Circuit Device Data Freescale Semiconductor V BUSWU 0.4 V SUP Dominant level T T PROPWL WAKE IRQ stays low until SPI reading command ON Mode Timing DD ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS 33903/4/5 29 ...

Page 30

... SPI, and can be turned ON or AUX OFF. V low threshold detection and over-current AUX information will disable V can generate INT OFF by default and must be turned ON by the SPI. AUX DD , and are reported in the SPI and AUX Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 31

... This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a Analog Integrated Circuit Device Data Freescale Semiconductor capacitor to gnd. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the V the MUX-OUT pin ...

Page 32

... INT pin from other ICs without extra consumption in unpowered mode. 5 V-CAN MCU MUX-OUT A M(*) S_ir (*)Optional current monitor is used REG regulator current copy DD resistor OFF mode. This allows the DD Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 33

... LIN, TXDL, RXDL AND LINTERM These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. Analog Integrated Circuit Device Data Freescale Semiconductor . In Low Power The MC33903 and MC33904 do not have a LIN interface. DD However, the MC33905S (S = Single) and MC33905D (D = Dual) contain 1 and 2 LIN interfaces, respectively ...

Page 34

... INIT reset or Reset mode. When device is in Debug, SPI command can be send without any time constraints with respect to watchdog external PNP OFF modes). Dedicated secured SPI Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 35

... In such mode, the DC output current is expected to be limited to 100 μ few mA, as the ECU is in reduced power operation mode. Analog Integrated Circuit Device Data Freescale Semiconductor Debug can be left by removing from the DEBUG pin SPI command (ref to MODE register). 5 V-CAN regulator default in debug mode. ...

Page 36

... IR INIT start T_ INIT (T_ = 256ms) INIT SPI write (0x5A00) (W/D refresh) NORMAL (4) W/D refresh by SPI start T_ WDN (T_ = config) WDN SPI if enable W/D refresh LOW POWER by SPI start T_ (2) WDL I- < (1.5 mA) I- > (1.5 mA) time Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 37

... A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. Analog Integrated Circuit Device Data Freescale Semiconductor MODE CHANGE - from Normal mode to Flash mode - from Normal mode to Reset mode (reset request). ...

Page 38

... PROPER RESPONSE TO INT A device detect, that upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two watchdog periods. Such feature must be enabled by SPI via the INIT watchdog register bit 7 Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 39

... INIT BATFAIL s_1 Normal mode s_11: write INT registers legend: Series of SPI Single SPI Figure 21. Power Up Normal and Low Power Modes Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL BLOCK OPERATION VERSUS MODE I/O AUX OFF OFF High-impedance HS/LS off OFF ...

Page 40

... Figure 22. Wake-up from Low Power Modes ON mode DD Based on reg configuration Based on reg configuration NORMAL ON REQUEST NORMAL DD pattern Stop FWU timer duration (50-8192 ms) SPI selectable I (3.0 mA typ) DD-OC I deglitcher or timer (100 us typ, 3 -32 ms Wake-up detected Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 41

... Figure 23. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch Analog Integrated Circuit Device Data Freescale Semiconductor CYCLIC SENSE OPERATION DURING LOW POWER MODES 400 μs, 800 μs, or 1.6 ms). The I/O-0 high side transistor or low side transistor can be activated. The selection is done by the state of I/O-0 prior to enter in low power mode ...

Page 42

... Leave Low Power V ON mode DD Cyclic INT period NORMAL REQUEST MODE ON and Cyclic INT due to improper operation DD INT Improper or no acknowledge SPI command SPI RST Cyclic INT period RESET and NORMAL REQUEST MODE MODE DD Analog Integrated Circuit Device Data Freescale Semiconductor ON DD ...

Page 43

... V remain ON until device SUP DD enters in Reset mode due under-voltage condition DD Analog Integrated Circuit Device Data Freescale Semiconductor The figures below illustrate the device behavior during V ramp up. As the Crank bit is by default set SUP1 enable when V V slew rate ...

Page 44

... Case 4: “V Behavior During V Ramp Down DD SUP1 (5.0 V) BATFAIL (3.0 V) 4.6 V”, with bit Cran (5 (typ 4.65 V) BATFAIL (3 (typ 3.2 V) DD_UV TH2 INT 3.2 V”, with bit Cran Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 45

... DD a wake-up event: in this safe state the device is automatically wakeable by CAN and I/O (if I/O wake-up was enable by the Analog Integrated Circuit Device Data Freescale Semiconductor BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION to properly control the device and properly refresh the watchdog) ...

Page 46

... AND I/O-1 low DBG - Reset low State B3 OFF AND I/O-1 low DBG AND Bus idle time out expired ON, SAFE pin remains low DD failure recovery, SAFE pin remains low < . SAFE pin is set low at same time R ST-TH Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 47

... RST OFF state SAFE 100 ms deglitcher time to activate SAFE and enter in SAFE mode to evaluate resistor at the DBG pin and monitor ECU external events Analog Integrated Circuit Device Data Freescale Semiconductor < 6.0 kohm), or Selection by the SPI DG step 2: Consequence on V 2nd 8th low ...

Page 48

... CAN bus idle time I/O-1 I/O-1 high to low transition step 3: Consequences for 8th RST SAFE V V < DD_UV TH GND RST SAFE V DD RST SAFE ON state > 10 kohm failure recovered DD V OFF DD If Reset s/c GND recovered V OFF DD Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 49

... ON. In this mode, the CAN lines are controlled by the TXD pin level, and the CAN bus state is reported on the RXD pin. Analog Integrated Circuit Device Data Freescale Semiconductor CAN INTERFACE CAN INTERFACE DESCRIPTION mode. An internal 2.5 V reference provide the 2.5 V recessive level via the matched R can be switched to GND in CAN Sleep mode ...

Page 50

... High ohmic termination (50 kohm) to GND Receiver (bus dominant set by other IC) Sleep or Stand-by mode pattern wake-up. The wake-up by the CAN is enabled or disabled via the SPI. resistor, the SPLIT IN . High-impedance Go to sleep, Normal or Listen Only mode Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 51

... BUS TERMINATION The device supports the two main types of bus terminations: • Differential termination resistors between CANH and CANL lines. • The figure below illustrate some of the most co Analog Integrated Circuit Device Data Freescale Semiconductor CANH Dominant Dominant Pulse # 1 Pulse # 2 CANL ...

Page 52

... Recessive level (2 Vrvb L5 CANL dominant level (1.4 V) Vr5 Hg (threshold 1. (threshold 1. (threshold V -2 (threshold V SUP CAN bus connect ECU connector No termination V BAT (12 (1.75 V) GND (0.0 V) Driver Dominant State Hg (threshold 1. -2 (threshold V -2.0 V) SUP SUP Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 53

... Excluding the internal propagation delay, the RXD output should be low when the differential receiver is low. In case of an external short to VDD at the RXD output, RXD will be tied to a high Analog Integrated Circuit Device Data Freescale Semiconductor Hg (threshold 1. (threshold 1. (threshold V -0.43 V) ...

Page 54

... The driver stays disabled until the failure is/are removed (TxD and/or RxD is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TxD/RxD mode in order to re enable the CAN bus driver. Analog Integrated Circuit Device Data Detection Freescale Semiconductor ...

Page 55

... LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. Analog Integrated Circuit Device Data Freescale Semiconductor LIN BLOCK LIN INTERFACE DESCRIPTION The LIN pin exhibits no reverse current from the LIN bus ...

Page 56

... LIN transmitter in recessive State TXDDOM LIN transmitter and receiver disabled LIN driver temperature > 160°C (typ) High Side turned off Figures 17 and 18. will restart if device was OFF DD DD RECOVERY Condition gone Condition gone Condition gone Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 57

... MISO S14 Tri-state S15 Analog Integrated Circuit Device Data Freescale Semiconductor HIGH LEVEL OVERVIEW • bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits: • bits (S15 to S8) are device status bits • bits (Do7 to Do0) are either extended device status bits, device internal control register content or device flags ...

Page 58

... Init W/D Init LIN I/O Init MISC SPE_MODE 1) Write to register to select device Specific mode, using “Inverted Note for Bit 8 P/N Functionality 2) Read back register “control bits” Random Code”. 2) Read “Random Code” Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 59

... PARITY BIT 8 Calculation The parity is used for write to register command (bit 15, calculated based on the number of logic one Analog Integrated Circuit Device Data Freescale Semiconductor TIM_A TIM_B TIM_C W/D MODE 1) Write to register to select Low Power mode, with optional “Inverted Random code” ...

Page 60

... The parity function is optional selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be “0”. Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 61

... The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0). Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 ...

Page 62

... POR Ram b6 Ram b5 Ram POR Ram c6 Ram c5 Ram POR Ram d6 Ram d5 Ram POR Bit 3 Bit 2 Bit 1 Bit 0 Ram a3 Ram a2 Ram a1 Ram Ram b3 Ram b2 Ram b1 Ram Ram c3 Ram c2 Ram c1 Ram Ram d3 Ram d2 Ram d1 Ram Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 63

... Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 bit 3 V rst[1] V rst[0] V rstD[1] V DDL ...

Page 64

... V (parameter V SUP1 SUP-TH1 V kept ON when V is below typ 4.0 V (parameter V DD SUP1 bit 3 bit 2 bit 1 bit 0 WD_spi[0] WD N/Win Crank threshold is defined in DD_OC_LP current > DD_OC_LP is falling toward GND SUP1 ), and device in Reset mode ) SUP_TH1 Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...

Page 65

... I/O_0 is actively set. Example: If I/0_0 high side is ON during active time, then I/O_O low side is turned ON at expiration of the active time, for the Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 ...

Page 66

... INT pin will assert a low level pulse, duration selected by bit [b4] INT pin assert a permanent low level (no pulse) INT width - Select the INT pulse duration Function disable (26) value. Function disable bit 2 bit 1 bit 0 Dbg Res[2] Dbg Res[1] Dbg Res[ Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 67

... MOSI : 0001 0011 0000 0000 [Hex:0x 13 00] MISO report 16 bits, random code are bits (5-0) miso = xxxx xxxx xxR5 (RxD = 6 bits random code) Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 bit 6 bit 5 ...

Page 68

... Cyc-int[2] Cyc-int[1] Cyc-int[ 101 110 111 96 192 384 128 256 512 101 110 111 192 384 768 258 512 1024 Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...

Page 69

... Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 WD-LP-F[2] WD-LP-F[1] WD-LP-F[0] FWU[ POR Watchdog in Low Power V ON Mode DD ...

Page 70

... Cyclic Sense OFF ON OFF ON Cyclic INT Watchdog OFF OFF OFF ON ON OFF ON ON OFF OFF OFF ON ON OFF ON ON OFF OFF OFF ON ON OFF ON ON OFF OFF OFF ON ON OFF ON ON Analog Integrated Circuit Device Data Freescale Semiconductor bit bit 0 N/A ...

Page 71

... Read device current mode, Keep DEBUG mode Release SAFE pin (turn OFF). MOSI in hexadecimal MISO reports Debug and SAFE state (bits 1,0) Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING OFF, the wake-up - leave Debug state - release or turn off SAFE pin ...

Page 72

... Debug mode OFF Debug mode Active bit 2 bit 1 bit 0 V bal en V bal auto V OFF N/A N/A N/A is disabled in case AUX is disabled in case detected AUX is disabled in case detected AUX is > typ turn OFF) DD Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 73

... Bits Disable Usage of Low Power V 0 Enable Usage of Low Power V 1 Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING Description OFF mode DD OFF mode DD SERIAL PERIPHERAL INTERFACE 33903/4/5 73 ...

Page 74

... Normal mode, the CAN state is controlled by bits 7 and 6. 33903/4/5 74 MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 CAN mod[0] Slew[1] Slew[0] Wake up 1 POR Description bit 3 bit 2 bit CAN int POR POR Analog Integrated Circuit Device Data Freescale Semiconductor bit 0 0 ...

Page 75

... I/O-0 driver disable, Wake-up capability disable 00 I/O-0 driver disable, Wake-up capability enable. 01 I/O-0 Low Side driver enable. 10 I/O-0 High Side driver enable. 11 Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 bit 3 I/O-3 [0] I/O-2 [1] ...

Page 76

... Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set activate the MCU INT request. 33903/4/5 76 MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 bit 3 MCU req LIN2 fail LIN1fail I POR Description (30) low or V over-current AUX AUX bit 2 bit 1 bit 0 SAFE - Vmon V-CAN Over-current, V AUX DD DD Analog Integrated Circuit Device Data Freescale Semiconductor (29 SUV ...

Page 77

... TXDL is low, will be ignored and the LIN interface remains disabled. 32. In order to use LIN interface, the 5V-CAN regulator must be ON. Analog Integrated Circuit Device Data Freescale Semiconductor DETAIL OF CONTROL BITS AND REGISTER MAPPING MOSI Second Byte, bits 7-0 bit 6 ...

Page 78

... MOSI Second Byte, bits 7-0 bit 6 bit 5 bit 4 LIN mode[0] Slew rate[1] Slew rate[ POR Description (33) is below typ 6.0 V. This is to meet J2602 specification SUP2 6.0 V, until 5 V-CAN is disabled. SUP2 bit 3 bit 2 bit 1 - LIN Vsup ext Analog Integrated Circuit Device Data Freescale Semiconductor bit 0 0 ...

Page 79

... V Interrupt example: MISO bit [7-0] = 1011 0010: MC33904, 5.0 V version, silicon pass 3.1 Analog Integrated Circuit Device Data Freescale Semiconductor FLAGS AND DEVICE STATUS • for I/O real time status, device identification and CAN LIN driver receiver real time state. • bit are the register address from which the flags read. • ...

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... SUP1 threshold, while device is in Normal mode. DD-OC recover and flag read (SPI) DD threshold LP, while device is in Low Power DD-OC Analog Integrated Circuit Device Data Freescale Semiconductor LIN1 bus dom clamp - LIN2 bus dom clamp - ...

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... Set: failure detected. Reset failure recovered and flag read (SPI) CANH to Description Report CAN H short to GND failure GND Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI) Analog Integrated Circuit Device Data Freescale Semiconductor SERIAL PERIPHERAL INTERFACE Description DOM failure BAT failure BAT ...

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... V SUP1-OV above threshold. Reset V SUP1 V SUP1-OV V SUP1 OFF mode was selected, prior wake-up occurred. DD OFF selected. Reset: Flag read (SPI) DD > thresh and flag read (SPI) V SUPUV < thresh and flag read (SPI) V SUPOV ON mode. DD Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 83

... W/D refresh Description Report that a wrong or missing W/D failure occurred. failure Set / Reset condition Set: failure detected. reset: flag read (SPI) Analog Integrated Circuit Device Data Freescale Semiconductor Description has reached over-temperature prewarning threshold. DD thermal sensor above threshold. Reset threshold. DDUV + 0 ...

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... Set: RxD high failure detected. Reset: failure recovered and flag read (SPI) TxD1/2 dom Description Report that TxD1/2 pin is shorted to GND. Set / Reset condition Set: TxD low failure detected. Reset: failure recovered and flag read (SPI) 33903/4/5 84 Description DOM Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... The INT RST source is from a Regulator event, flag from REG register sub adress high (bit VREG-1 The INT RST source is from a Regulator event, flag from REG register sub adress low (bit VREG-0 Analog Integrated Circuit Device Data Freescale Semiconductor One Byte Fix Status: when a device read operation is performed (MOSI bits 15-14, bits 11). 11 ...

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... RXDL2 LIN1 LIN TERM2 LIN2 GND SAFE * = Option RF module Switch Detection Interface eSwitch Safing Micro Controller * CAN xcvr RST INT A/D MCU SPI CAN LIN1 LIN2 V V SUP SUP Safe Circuitry Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... LIN BUS 1 option 2 option 1 Notes 36. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 40. 33905S Typical Application Schematic Analog Integrated Circuit Device Data Freescale Semiconductor Q2 5.0 V (3.3 V) >2.2 μF <10 k VBAUX VCAUX VAUX VE ...

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... RXD I/O-3 CANH SPLIT CANL GND SAFE * = Option RF module Switch Detection Interface eSwitch Safing Micro Controller CAN xcvr V DD RST INT A/D MCU SPI CAN V V SUP SUP OR function Safe Circuitry Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 89

... CAN BUS Notes 38. Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor > 10 μF on VSUP1/VSUP2 pins Figure 42. 33903 Typical Application Schematic Analog Integrated Circuit Device Data Freescale Semiconductor VSUP1 VSUP2 VDD DBG >1.0 μF RST 5V-CAN INT ...

Page 90

... VAUX VE VB VDD External Transistor - No VAUX Figure 43. Application Options and DD Q2 5.0 V/3.3 V VBAUX VCAUX VAUX Q1 VSUP2 VE VSUP1 VB VDD Partial View ex2: Split V Supply SUP VBAUX VCAUX VAUX VSUP2 VE VSUP1 VB VDD Partial View Analog Integrated Circuit Device Data Freescale Semiconductor BAT ...

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... For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D PACKAGING SOIC 32 PACKAGE DIMENSIONS ...

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... PACKAGING SOIC 32 PACKAGE DIMENSIONS 33903/4 SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D PACKAGING SOIC 32 PACKAGE DIMENSIONS 33903/4/5 93 ...

Page 94

... PACKAGING SOIC 54 PACKAGE DIMENSIONS 33903/4/5 94 SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 95

... Analog Integrated Circuit Device Data Freescale Semiconductor EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D PACKAGING SOIC 54 PACKAGE DIMENSIONS 33903/4/5 95 ...

Page 96

... PACKAGING SOIC 54 PACKAGE DIMENSIONS 33903/4 SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor ...

Page 97

... Added V • Added • Revised • Revised • Added Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY Cyclic INT Operation During Low Power VDD ON Mode on page 42 Drop voltage without external PNP pass transistor to VDD Voltage regulator, VDD pin on page SUP1-3 ...

Page 98

... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc ...

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