MCZ33989EG Freescale Semiconductor, MCZ33989EG Datasheet
MCZ33989EG
Specifications of MCZ33989EG
Available stocks
Related parts for MCZ33989EG
MCZ33989EG Summary of contents
Page 1
... Figure 1. MC33989 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. Device Switch Allowing BAT MC33989DW/R2 MCZ33989EG/R2 V PWR 33989 VDD1 VSUP GND V2CTRL RST ...
Page 2
... VSUP Monitor Dual Voltage Regulator VDD1 Monitor HS1 Control Oscillator Interrupt Watchdog Reset Programmable Wake-Up Inputs Mode Control Interface High Speed 1.0 MB/s CAN Physical V 2 Interface V2CTRL V2 VDD1 INT WD RST CS SCLK SPI MOSI MISO GND Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 3
... HS1 Output 14–17 L0:L3 Input 22 CANH Output 23 CANL Output 24 SCLK Input 25 MISO Output 26 MOSI Input 27 CS Input 28 WD Output Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS VDD1 3 26 MOSI RST 4 25 MISO INT 5 24 SCLK GND 6 23 GND GND ...
Page 4
... SUP I Internally Limited - 4.0 to 4.0 ESDH -2.0 to 2.0 ESDM ±200 WUDC -0 -2.0 to 2.0 -100 to 100 - CANH/L 200 CANH/L 40 TRH/L - TRH/L V -0.5 to 6.0 -4.0 to 4.0 ESDCH ESDCM -200 to 200 ZAP Table 17, page 35. Analog Integrated Circuit Device Data Freescale Semiconductor Unit 200 pF, ...
Page 5
... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standerd J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Analog Integrated Circuit Device Data Freescale Semiconductor Symbol (5) R Θ (6) ...
Page 6
... V V — — — — — — 42.5 45 µA — 72 105 µA — µA — 100 150 µA — 135 210 µA — 130 210 µA — 160 230 1.5 3.0 4.0 V Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 7
... DD1 (tantalum capacitor). In reset, normal request, normal and standby modes. Measure with µF Tantalum. 15. Guaranteed by design; however not production tested. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 40°C ≤ T ≤ 125°C, GND = 0 V unless otherwise noted. Typical SUP A = 25°C under nominal conditions unless otherwise noted. ...
Page 8
... V DD1 0.99 1.0 1.01 mA 200 — — mA 0.0 — 10 3.75 4.0 4. 0.0 — 1 — V DD1-0.9 DD1 µA -2.0 — 2.0 ” parameter. DDst-cap and prevent the device to stay in DDSWU Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 9
... Push/Pull structure with tri-state condition CS high. 22. Output pin only. Supply from VDD1. Structure switch to ground with pull-up current source. Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS ≤ 40°C ≤ T ≤ 125°C, GND = 0 V unless otherwise noted. Typical ...
Page 10
... I DOM — I SLEEP — I DIS — Analog Integrated Circuit Device Data Typ Max Unit V 2.5 3.0 3.0 3.6 3.2 3.7 V 3.3 3.8 4.0 4.6 4.2 4.7 V — 1.3 µA — 1.5 3.0 mA 2.0 6.0 µ µA — 1.0 Freescale Semiconductor ...
Page 11
... TX High Level Input Current, VTX = Low Level Input Current, VTX = Output Voltage High, IRX = 250 µA RX Output Voltage Low, IRX = 1.0 mA Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS ≤ 40°C ≤ T ≤ 125°C, GND = 0 V unless otherwise noted. Typical SUP A = 25° ...
Page 12
... N — N/A ns — — — — 50 — — — — 50 µs 18 — 34 µs 7 kHz — 100 — kHz — 100 — ms 8.58 9.75 10.92 ms 39 100 112 ms 308 350 392 % -12 — 12 Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 13
... Normal Mode Notes 25. Delay starts at falling edge of clock cycle #8 of the SPI command and start of Turn ON or Turn OFF of HS1 or V2. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 40°C ≤ T ≤ 125°C, GND = 0 V unless otherwise noted. Typical SUP A = 25° ...
Page 14
... Freescale Semiconductor ...
Page 15
... GND Note: Waveform in accordance to ISO 7637 part1, test pulses and 3b. Figure 5. Transient Test Pulse for L0:L3 Inputs Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 40°C ≤ T ≤ 125°C, GND = 0 V unless otherwise noted. Typical SUP A = 25°C under nominal conditions unless otherwise noted. ...
Page 16
... ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS T LRD 2 0 0.8 V 33989 16 T TRD TX 0 0.9 V DIFF T LDR 0 DIFF T RRD RX 0.8 V Figure 7. Transceiver AC Characteristics 2 TDR 0 DIFF CANH CANL T RDR 0.5 V 2.0 V Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 17
... VALID t SOEN MISO Notes: Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge. Outgoing data at MISO pin is set by the SBC at SCLK rising edge (after t Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS t PCLK t WCLKL t SIH Di 0 Don’t Care Do 0 Figure 8 ...
Page 18
... SCLK is the System Clock input pin of the serial peripheral interface. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 19
... MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS the Chip Select pin of the serial peripheral interface. ...
Page 20
... The objective is to maintain the MCU of the application supplied while it is turned into power saving condition (i.e Stop or Wait modes). In Stop mode the device supply current from V is very low. BAT Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 21
... Normal Request modes etc. In case the Normal Request mode is entered after a wake- up from Sleep mode, and configuration occurs while Analog Integrated Circuit Device Data Freescale Semiconductor the SBC is in Normal Request mode, the SBC goes back to Sleep mode. APPLICATION WAKE-UP FROM SBC SIDE When an application is in Stop mode, it can wake-up from the SBC side ...
Page 22
... DD1 ), the ret pin is pulled low until STTH . DUR) WD Output Reset Output Low to High Low to High High High High Low Low (Note) Low High High High Low Low (Note) High Analog Integrated Circuit Device Data Freescale Semiconductor DD1 ...
Page 23
... Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after reset or power-up, is Mode 1. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS In both modes reset is active at device power-up and wake-up. • ...
Page 24
... Running if Enabled Low Power Not Running if Wake-up Capability Disabled DD1S/WU if Enabled Not Running Low Power Wake-up Capability if Enabled Not Running Same as Normal Not Running Same as Standby Not Running Same as Stop Not Operating Not Operating Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 25
... HS1 VSUP switch. The HS1 switch is activated in Sleep or Stop modes from an Analog Integrated Circuit Device Data Freescale Semiconductor RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS Watchdog Period internal timer ...
Page 26
... V time reset is low, the reset pin sinks 5.0 mA maximum (L parameter). Figure 16. Figure 15 SBC Not in Debug Mode and WD ON time (3.4 ms typical) DUR for 350 ms typical. During the DD1 Analog Integrated Circuit Device Data Freescale Semiconductor SUP PDW ...
Page 27
... WD: Trigger = TIM1 register write operation. Figure 13. State Machine (Not Valid in Debug Modes) Notes These two SPI commands must be sent consecutively in this sequence. 30 activated. Analog Integrated Circuit Device Data Freescale Semiconductor RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS VDD1 RST SBC WD V External supply and sources applied to and WD test points on application circuit board ...
Page 28
... Figure 14. Behavior at SBC Power-Up WD: Timeout 350 ms Reset Counter Reset (3.4 ms) Expired SPI: MCR (0000) & Normal Debug SPI: MCR (0000) & Stand-by Debug Figure 15. Transitions to Enter Debug Modes Power Down Normal Debug Stand-by Debug Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 29
... Reset condition is the condition causing the bit to be set at the reset value. Table 7. Data Format Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit R Analog Integrated Circuit Device Data Freescale Semiconductor WD: Time-out 350 ms Reset Counter (3.4 ms) Expired R R Stand- SPI: Stand-by Debug SPI: Normal Debug ...
Page 30
... Write: TIM2, Cyclic sense and force wake-up timing selection Write: Control HS1 periodic activation in Sleep and Stop modes, force Low Power Mode wake-up Control Register Write: Interrupt source configuration Interrupt Register Read: INT source Comment and Use and V2 Low status SUP Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 31
... Logic OR of CAN Failure (TXF Permanent Dominant, or CAN Over Current or CAN thermal), or HS1 Over GFAIL Temperature Low Battery Fail Flag (set when V BATFAIL Temperature Pre-Warning on V VDDTEMP Watchdog Reset Occurred WDRST Analog Integrated Circuit Device Data Freescale Semiconductor D3 D2 — MCTR2 (31) BATFAIL VDDTEMP — 0 — ...
Page 32
... Reset Threshold 2 Selected (typ 4 — SC1 CANWU TXF — 0 — POR D1 D0 SAFE RSTTH 0 0 POR POR Condition Device Power-Up V1 Normal, WD Properly Triggered V1 Drops Below R STTH WD Timeout Description D1 D0 SC0 MODE CUR THERM 0 0 POR POR Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 33
... When HS1 is turned OFF due to an over temperature condition, it can be turned ON again by setting the Analog Integrated Circuit Device Data Freescale Semiconductor mode, and controls the wake-up option (wake-up enable or disable) when the CAN module is in Sleep mode. CAN module modes (Normal and Sleep) are independent of the 16 ...
Page 34
... L0/L1 Config 0 Inputs Disabled 1 High Level Sensitive 0 Low Level Sensitive 1 Both Level Sensitive x — Description 21 LCTR1 LCTR0 L1WU L0WU 0 0 Table 22. L2/L3 Config — Inputs Disabled High Level Sensitive Low Level Sensitive Both Level Sensitive Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 35
... R Reset Value Reset Condition Analog Integrated Circuit Device Data Freescale Semiconductor 2. TIM2–is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is read operation it is not allowed in either TIM1 or TIM2 registers. Please see ...
Page 36
... Cyclic Sense/FWU Timing 5 Cyclic Sense/FWU Timing 6 Cyclic Sense/FWU Timing 7 Cyclic Sense/FWU Timing — HS1AUTO — — — 0 — POR, NR2R N2R,STB2RSTO2R Auto Timing HS1 in Sleep and Stop Modes OFF ON, HS1 Cyclic, Period Defined in TIM2 Register Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 37
... Below 6 SUP SUPLOW If HS1 - V2 interrupt is only selected (only bit D2 set OT LOW in INT register), reading INT register bit D2 leads to two possibilities: Analog Integrated Circuit Device Data Freescale Semiconductor D3 D2 VSUPLOW HS1OT-V2LOW VSUPLOW HS1OT 0 0 POR, RST POR, RST Description Medium Temperature (Pre-Warning) DD Below 6 ...
Page 38
... CL CS Figure 20. Typical Application Diagram V2CTRL C10 C5 V2 Vdd1 5V/200mA Mode control Oscillator INT Int WD Watchdog RST Reset MOSI SCLK MCU SPI Interface MISO GND Safe Circuitry C4: 100nF C5: 47uF tantal C6,C7,C8,C9,C10: 100nF CL, CH: 220 pF Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 39
... Wake-Up on page 49 FAILURE ON V2 SUPPLY, CAN BUS LINES, AND TX PIN V2LOW on page 51 TX Permanent Dominant on page 51 Analog Integrated Circuit Device Data Freescale Semiconductor SUPPLEMENTAL APPLICATION NOTES CAN Driver Overtemperature: on page 52 Overcurrent Detection: on page 52 Protection on page 52 Current in Case of Bus Short Conditions on page 52 ...
Page 40
... Figure 22. V2 Regulator Operation Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF C5: >10uF C6: 100nF VDD R1: 2.2k Rt 120 Rp0 to Rp3: 22k Rs0 to Rs3 CL0 to CL3: 10nF Q1: MJD32C MCU Figure 22. Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF VDD Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 41
... Reset every 350 ms Figure 24. Power Up and V Analog Integrated Circuit Device Data Freescale Semiconductor 350 watchdog is written (no TIM1 register write) a reset occurs, and the SBC returns to normal request mode.During this sequence WD is active (low level). Once watchdog is written the SBC goes to normal mode: ...
Page 42
... The following case describes the signal for CAN wake up. Refer to page and the TCAN analysis. ) follows the V OH and V2 are off (The DD1 is shorted DD1 No problem on Watchdog period for more details on CAN wake up signals Analog Integrated Circuit Device Data Freescale Semiconductor DD1 ...
Page 43
... The total time is 11.5 ms (for a cyclic sense total time of 5 ms) in this example. WAKE-UP TIMING: STOP MODE The following paragraphs describe the wake-up events from stop mode, and the sequence of the signals at the SBC Analog Integrated Circuit Device Data Freescale Semiconductor t1 t2 Figure 27. CAN Wake-Up LX with Cyclic Sense turn on): typ ...
Page 44
... Figure 31. CS Wake-Up Overcurrent Wake-Up The following figure describes the signal when an overcurrent is detected at V will lead to a wake-up from stop mode. SBC ready to accept SPI command. SBC ready to accept SPI command overcurrent condition DD1 DD1 Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 45
... T2 the same than Lx to INT pulse: typ 100 µs • The total time is around 5.13 ms (for a cyclic sense total time of 5 ms) in the above example. Analog Integrated Circuit Device Data Freescale Semiconductor t INT + t S-1STSPI (33µs max) t2 Wake-up signalled to MCU. Figure 32. Overcurrent Wake-Up • ...
Page 46
... If “CANH minus CANL” is above the threshold, the bus is dominant and RX is set low. This is illustrated in the figure below. TX CANH-DOM CANH CANH-REC 2.5V CANH-CANL CANL-REC 2.5V CANL CANL-DOM RX CANH line Bus termination (60 ohms) CAN L line Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 47
... CANL Gnd Differential termination concept Analog Integrated Circuit Device Data Freescale Semiconductor Normal Mode and Slew Rate Selection The slew rate selection is done via the SPI. Four slew rates are available. The slew rate affects the recessive to dominant and dominant to recessive transitions. This affect is also the delay time from the TX pin to the bus, and from the bus to RX ...
Page 48
... Floating to gnd LOW Floating to gnd Same as normal Same as normal mode mode 5 V Floating to gnd LOW Floating to gnd LOW Floating to gnd Components list: C1: 22uF, C2: 100nF C3: >10uF C4: 100nF Rt: 60 ohms Signal generator F<500kz (1Mb/s) Signal at RX output Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 49
... If the SBC is in normal or standby mode, and the CAN interface is in sleep mode with wake-up enabled, the CAN Analog Integrated Circuit Device Data Freescale Semiconductor In low power mode the CANH and CANL driver are disabled, and the receiver is also disabled. CANH and CANL have a typical 50 k ohm impedance to gnd ...
Page 50
... CAN wake-up occurs in sleep or stop mode. TX sending node. VDD start CAN bus CAN wake-up: SBC in stop mode. INT pulse Figure 41. SBC Key Signals CANH-DOM CANH-DOM Pulse # 2 Pulse # 3 CANL-DOM CANL-DOM Incoming CAN message Internal wake-up signal INT Terminal Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 51
... V1 below the V1 under voltage reset, typ 4.6 V), the device will enter the reset mode. The V2LOW flag will also be set. In this case, the Analog Integrated Circuit Device Data Freescale Semiconductor Stuff bit 5 recessive bits Stuff bit 1 recessive bit ...
Page 52
... CAN supply, the CAN line can be different from the nominal case. The various cases. V2 Terminal I_H CANH line CANH 60 ohms I_TERM CANL CAN L line I_L Figure 44 and Table 35 describe the VBAT 5V VBAT 5V Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 53
... RX, so the CAN protocol handler inside the MCU increases its TEC «transmit error counter» by 8.The sender node keeps driving TX in dominant until it reaches the error passive level (TEC=128). Analog Integrated Circuit Device Data Freescale Semiconductor I-L current Normal communication communication ...
Page 54
... TEC reaches 255: the node is BUS OFF Figure 46. Node is in Bus Off State in order to control the device. Structure of the Byte: ADR (3 bits) + R/W (1bit) + DATA (4 bits). MSB is sent first. Refer to MC33989 specifications for more details. BUS OFF is recover Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 55
... How to Set the CAN Interface in Sleep Mode How to Control HS1 Output CAN in normal CAN in Sleep Analog Integrated Circuit Device Data Freescale Semiconductor • read LX wake-up flag Read WUR ($80) • Write watchdog Write TIM1 =$ the period of the watchdog ex:$00 for 10 ms • Clear V2low, Vsuplow flags Read IOR ($60) • ...
Page 56
... Force wake-up period Figure 54. Force Wake-Up • Disable Force wake-up,LX cyclic • Disable LX • CAN sleep and CAN wake-up disable note: can interface will enter sleep mode as soon as $53 is sent Figure 55. Disable all Wake-Up Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 57
... How to Enter in Stop Mode without Watchdog SBC in normal or Standby SBC in Stop Analog Integrated Circuit Device Data Freescale Semiconductor • Bit NoStop=»1»: sleep mode is allowed Write RCR= $34 • SBC and CAN module go to sleep mode Write MCR =$14 it will sleep on the rising edge of CS Figure 56. Enter Sleep Mode • ...
Page 58
... WUR =XX? • Wake-up from LX NO Was FWU YES • Force wake-up enabled? NO Was any SPI YES • CS wake-up command sent? NO YES Vsuplow in IOR • VBAT undervoltage (<6.1 V) leading register =»1»? a VDD1 undervoltage reset NO Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 59
... How to Distinguish Between V2LOW and HS1 Overtemperature Read IOR ($60) Figure 61. Distinguish Between V2LOW and HS1 Overtemperature Analog Integrated Circuit Device Data Freescale Semiconductor • In order to identified the source of the interruption Read INTR ($E0) note: V2 and HS1-OT are merged in the same bit • ...
Page 60
... PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. 33989 60 PACKAGING PACKAGE DIMENSIONS DW SUFFIX EG SUFFIX (Pb-Free) 28-PIN 98ASB42345B ISSUE G Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 61
... Analog Integrated Circuit Device Data Freescale Semiconductor DW SUFFIX EG SUFFIX (Pb-Free) 28-PIN 98ASB42345B ISSUE G PACKAGING PACKAGE DIMENSIONS 33989 61 ...
Page 62
... Figure 62. Surface Mount for SOIC Wide Body 33989DWB 33989EG 28-PIN SOICW DWB SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW Note For package dimensions, refer to the 33989 device datasheet. 28 Terminal SOICW 1.27 mm Pitch 18 7.5 mm Body non-Exposed Pad Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 63
... Outline 100 mm board area, including edge connector for thermal testing Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Analog Integrated Circuit Device Data Freescale Semiconductor A Figure 63. Thermal Test Board Table 37. Thermal Resistance Performance Thermal Resistance R θ the thermal resistance between die junction and θ ...
Page 64
... W Step response, Device on Thermal Test Board Area A = 600 (mm 33989 θJA 0 300 Heat spreading area A [mm²] Figure 64. Device on Thermal Test Board θJA 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 65. Transient Thermal Resistance R 600 θJA θ Analog Integrated Circuit Device Data Freescale Semiconductor ...
Page 65
... Updated to the prevailing Freescale form and style 6/2006 10.0 • Updated from Advance Information to Final documentation • Removed PC33989EG/R2 and replaced with MCZ33989EG/R2 in the Ordering Information block • Replaced the label Logic Inputs with 11/2006 11.0 RST, WD, and INT) on page 4 • ...
Page 66
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...