PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet
PI7C8140AMAE
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PI7C8140A 2-Port PCI-to-PCI Bridge REVISION 1.01 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
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REVISION HISTORY DATE REVISION NUMBER 11-13-2003 0.01 03-04-2004 0.02 03-24-2004 0.03 05-07-2004 1.00 03-20-2007 1.01 PREFACE The PI7C8140A datasheet will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. ...
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This page intentionally left blank. 07-0067 2-PORT PCI-TO-PCI BRIDGE Page March 20, 2007 – Revision 1.01 PI7C8140A ...
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TABLE OF CONTENTS 1 SIGNAL DEFINITIONS.............................................................................................................................11 1.1 SIGNAL TYPES....................................................................................................................................11 1.2 SIGNALS ..............................................................................................................................................11 1.2.1 PRIMARY BUS INTERFACE SIGNALS ...................................................................................11 1.2.2 SECONDARY BUS INTERFACE SIGNALS .............................................................................12 1.2.3 CLOCK SIGNALS ........................................................................................................................14 1.2.4 MISCELLANEOUS SIGNALS ....................................................................................................14 1.2.5 POWER AND GROUND..............................................................................................................14 1.3 PIN LIST – ...
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VGA SUPPORT ....................................................................................................................................37 3.4.1 VGA MODE ..................................................................................................................................37 3.4.2 VGA SNOOP MODE ....................................................................................................................38 4 TRANSACTION ORDERING ...................................................................................................................38 4.1 TRANSACTIONS GOVERNED BY ORDERING RULES.................................................................38 4.2 GENERAL ORDERING GUIDELINES...............................................................................................39 4.3 ORDERING RULES .............................................................................................................................39 4.4 DATA SYNCHRONIZATION .............................................................................................................41 5 ERROR HANDLING ..................................................................................................................................41 5.1 ...
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REGISTER TYPES ...............................................................................................................................59 13.2 CONFIGURATION REGISTER...........................................................................................................59 13.2.1 VENDOR ID REGISTER – OFFSET 00h ..................................................................................60 13.2.2 DEVICE ID REGISTER – OFFSET 00h....................................................................................60 13.2.3 COMMAND REGISTER – OFFSET 04h ...................................................................................60 13.2.4 PRIMARY STATUS REGISTER – OFFSET 04h ......................................................................61 13.2.5 REVISION ID ...
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MISCELLANEOUS CONTROL REGISTER – OFFSET C0h ..............................................78 14 ELECTRICAL AND TIMING SPECIFICATIONS ............................................................................79 14.1 MAXIMUM RATINGS.........................................................................................................................79 14.2 DC SPECIFICATIONS .........................................................................................................................79 14.3 AC SPECIFICATIONS .........................................................................................................................80 14.4 66MHZ TIMING ...................................................................................................................................81 14.5 33MHZ TIMING ...................................................................................................................................81 14.6 POWER CONSUMPTION....................................................................................................................81 15 PACKAGE INFORMATION.................................................................................................................82 15.1 ...
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... INTRODUCTION Product Description The PI7C8140A is Pericom Semiconductor’s PCI-to-PCI Bridge, designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8140A supports synchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz ...
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This page intentionally left blank. Page PI7C8140A 2-PORT PCI-TO-PCI BRIDGE March 20, 2007 – Revision 1.01 ...
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SIGNAL DEFINITIONS 1.1 SIGNAL TYPES SIGNAL TYPE STS OD 1.2 SIGNALS Signals that end with “#” are active LOW. 1.2.1 PRIMARY BUS INTERFACE SIGNALS Name Pin Number P_AD[31:0] 121, 122, 123, 124, 125, 126, 127, ...
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Name Pin Number P_TRDY# 17 P_DEVSEL# 18 P_STOP# 19 P_IDSEL 4 P_PERR# 21 P_SERR# 22 P_REQ# 119 P_GNT# 118 P_RST# 116 1.2.2 SECONDARY BUS INTERFACE SIGNALS Name Pin Number S_AD[31:0] 95, 94, 92, 91, 90, 89, 88, 87, 85, 83, ...
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Name Pin Number S_PAR 67 S_FRAME# 74 S_IRDY# 73 S_TRDY# 72 S_DEVSEL# 71 S_STOP# 70 S_PERR# 69 S_SERR# 68 S_REQ#[3:0] 99, 98, 97, 96 S_GNT#[3:0] 104, 103, 101, 100 S_RST# 105 07-0067 2-PORT PCI-TO-PCI BRIDGE Type Description TS Secondary Parity: ...
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CLOCK SIGNALS Name Pin Number P_CLK 117 S_CLKOUT[3:0] 110, 109, 108, 107 P_CLKRUN# 115 S_CLKRUN# 112 1.2.4 MISCELLANEOUS SIGNALS Name Pin Number ENUM# 113 LOO 114 SCAN_TM# 65 SCAN_EN 106 1.2.5 POWER AND GROUND Name Pin Number VDD 1, ...
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PIN LIST – 128-PIN QFP Pin Number Name 1 VDD 3 P_CBE#[3] 5 P_AD[23] 7 P_AD[21] 9 P_AD[19] 11 VSS 13 P_AD[16] 15 P_FRAME# 17 T_RDY# 19 P_STOP# 21 P_PERR# 23 P_PAR 25 P_AD[15] 27 P_AD[13] 29 VSS 31 ...
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Pin Number Name 115 P_CLKRUN# 117 P_CLK 119 P_REQ# 121 P_AD[31] 123 P_AD[29] 125 P_AD[27] 127 P_AD[25] 2 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across the bridge, and transaction termination. The bridge has two ...
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The bridge does not respond to special cycle transactions. The bridge cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as ...
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MEMORY WRITE TRANSACTIONS Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions. When the bridge determines that a memory write transaction forwarded across the bridge, the bridge asserts DEVSEL# with medium ...
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If offset 74h bits [8:7] = 00, the bridge converts Memory Write and Invalidate transactions to Memory Write transactions at the destination. If the value in the cache line size register does meet the memory write and invalidate conditions, the ...
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The bridge also conditionally asserts P_SERR# (see Section 5.4). 2.5.4 WRITE TRANSACTION BOUNDARIES The bridge imposes internal address boundaries when accepting write data. The aligned address boundaries are used ...
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PREFETCHABLE READ TRANSACTIONS A prefetchable read transaction is a read transaction where the bridge performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist ...
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READ PREFETCH ADDRESS BOUNDARIES The bridge imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the bridge stops pre-fetched data, unless the target signals a target disconnect before ...
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DELAYED READ COMPLETION WITH TARGET ...
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The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB (Read Data Buffer), the remaining ...
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In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. 2.7.1 TYPE 0 ACCESS TO PI7C8140A The configuration space is accessed by a Type 0 configuration transaction on the primary ...
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Leaves unchanged the function number and register number fields. The bridge asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on ...
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The bus command is a configuration read or write transaction. The bridge also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when ...
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Normal termination Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target. ...
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If the bridge is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. 2.8.2 MASTER ABORT RECEIVED BY PI7C8140A If the initiator initiates a transaction ...
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Bridge completes at least one data transfer. Bridge receives a master abort. Bridge receives a target abort. 24 The bridge makes 2 (default Table 2-7. Delayed Write Target Termination Response Target Termination Response Normal Returning disconnect to initiator ...
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DELAYED READ TARGET TERMINATION RESPONSE When the bridge initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 2-9 shows the ...
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Use more than 16 clocks to accept this transaction. For delayed read transactions: The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been ...
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ADDRESS DECODING The bridge uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ...
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I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change ...
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Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, the bridge forwards upstream those I/O ...
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Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the ...
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Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset ...
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VGA SNOOP MODE The bridge provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from the bridge needs to snoop or respond to VGA palette ...
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Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction ...
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Table 4-1. Summary of Transaction Ordering Pass Posted Write Posted Write No Delayed Read Request No Delayed Write Request No Delayed Read No Completion Delayed Write Yes Completion Note: The superscript accompanying some of the table entries refers to any ...
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DATA SYNCHRONIZATION Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.2, provides the following alternative methods for synchronizing data and interrupts: The device signaling the interrupt performs a read ...
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When the bridge detects an address parity error on the secondary interface, the following events occur: If the parity error response bit is set in the bridge control register, the bridge does not claim the transaction with S_DEVSEL#; this may ...
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Bridge completes the transaction normally. For upstream transactions, when the bridge detects a read data parity error on the primary bus, the following events occur: Bridge asserts P_PERR# two cycles following the data transfer, if the primary interface parity error ...
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For downstream transactions, when the bridge is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: The bridge sets the secondary interface data parity detected bit in the secondary ...
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For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: Bridge asserts S_PERR# two cycles after the data ...
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The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary ...
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Secondary Transaction Type Detected Parity Error Bit 0 Delayed Write 0 Delayed Write 1 Delayed Write X = don’t care Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is set under the ...
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Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions: The bridge is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be ...
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The bridge has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. The bridge did not detect the parity error as a target of the posted write transaction. The parity error ...
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Delayed read data cannot be transferred from target after 2 received) Master timeout on delayed transaction The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the ...
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S_IRDY# is asserted, the arbiter can be de-asserted one grant and asserted another grant during the same PCI clock cycle. 6.2.1 PREEMPTION Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit ...
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SECONDARY CLOCK OUTPUTS The bridge has 4 secondary clock outputs, S_CLKOUT[3:0] that can be used as clock inputs for up to four external secondary bus devices. The S_CLKOUT[3:0] outputs are derived from P_CLK. The secondary clock edges are delayed ...
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PCI POWER MANAGEMENT The bridge incorporates functionality that meets the requirements of the PCI Power Management Specification, Revision 1.1. These features include: PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism Support for D0 ...
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SECONDARY INTERFACE RESET The bridge is responsible for driving the secondary bus reset signals, S_RST#. The bridge asserts S_RST# when any of the following conditions are met: Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# ...
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PRIMARY INTERFACE P_CBE [3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory ...
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P_CBE [3:0] Command 1110 Memory Read Line 1111 Memory Write and Invalidate 11.2 SECONDARY INTERFACE S_CBE[3:0] Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 ...
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Initiator Master on Primary Master on Primary Master on Secondary Master on Secondary Master on Secondary 12.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 12.2.1 MASTER ABORT Master abort indicates that when the bridge acts as a master and receives no ...
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Master Abort. 12.2.4 SECONDARY IDSEL MAPPING When the bridge detects a Type 1 configuration transaction for a device connected to the ...
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CONFIGURATION REGISTERS PCI configuration defines a 64-byte DWORD to define various attributes of PI7C8140A as shown below. 13.1 REGISTER TYPES REGISTER TYPE RO RW RWC RWR RWS 13.2 CONFIGURATION REGISTER 31 – 24 Device ID Primary Status Class Code ...
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Reserved 13.2.1 VENDOR ID REGISTER – OFFSET 00h Bit Function Type 15:0 Vendor ID RO 13.2.2 DEVICE ID REGISTER – OFFSET 00h Bit Function Type 31:16 Device ID RO 13.2.3 COMMAND REGISTER – OFFSET 04h Bit Function ...
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Bit Function Type Wait Cycle 7 RO Control P_SERR enable Fast Back-to Back Enable 15:10 Reserved RO 13.2.4 PRIMARY STATUS REGISTER – OFFSET 04h Bit Function Type 19:16 Reserved RO 20 Capabilities RO List 21 66MHz ...
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REVISION ID REGISTER – OFFSET 08h Bit Function Type 7:0 Revision RO 13.2.6 CLASS CODE REGISTER – OFFSET 08h Bit Function Type 15:8 Programming RO Interface 23:16 Sub-Class Code RO 31:24 Base Class RO Code 13.2.7 CACHE LINE REGISTER ...
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SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function Type 15:8 Secondary Bus RW Number 13.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h Bit Function Type 23:16 Subordinate RW Bus Number 13.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...
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Bit Function Type 15:12 I/O Limit RW Address [15:12] 13.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function Type 20:16 Reserved RO 21 66MHz RO Capable 22 Reserved RO Fast Back-to Back Capable Data Parity 24 RWC Error ...
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Bit Function Type 15:4 Memory Base RW Address [15:4] 13.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h Bit Function Type 19:16 Reserved RO 31:20 Memory Limit RW Address [31:20] 13.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h Bit Function ...
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PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch Bit Function Type 31:0 Prefetchable RW Memory Limit Address, Upper 32-bits [63:32] 13.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h Bit Function Type 15:0 I/O Base RW ...
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BRIDGE CONTROL REGISTER – OFFSET 3Ch Bit Function Type 16 Parity Error RW Response 17 S_SERR# RW enable 18 ISA enable RW 19 VGA enable RW 20 Reserved R/O 21 Master Abort RW Mode 22 Secondary RW Interface Reset ...
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Bit Function Type 24 Primary Master R/W Timeout 25 Secondary RW Master Timeout 26 Master Timeout RWC Status 27 Discard Timer RW P_SERR# enable 31-28 Reserved RO 13.2.29 SUBSYSTEM VENDOR ID REGISTER – OFFSET 40h Bit Function Type 15:0 Subsystem ...
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Bit Function Type 1 Memory Write RW Disconnect Control 3:2 Reserved RO 4 Secondary Bus RW Prefetch Disable 7:5 Reserved RO 8 Chip Reset RWR 9 Test Mode 1 RW 11:10 Test Mode Test Mode 3 RW ...
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ARBITER CONTROL REGISTER – OFFSET 44h Bit Function Type 19:16 Arbiter Control RW 24:20 Reserved RO 25 Priority of RW Secondary Interface 31:26 Reserved RO 13.2.33 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit Function Type Memory Read 0 ...
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Bit Function Type Memory Read 4 Data Buffer RW Control 15:5 Reserved RO 13.2.34 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch Bit Function Type Secondary bus arbiter 31:28 RW preemption control 13.2.35 P_SERR# EVENT DISABLE REGISTER – OFFSET ...
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Bit Function Type Target Abort 3 During Posted RW Write Master Abort 4 On Posted RW Write Delayed Write 5 RW Non-Delivery Delayed Read – Data From RW Target 7 Reserved RO 13.2.36 SECONDARY CLOCK CONTROL REGISTER – ...
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Bit Function Type 5:4 Clock 2 disable RW 7:6 Clock 3 disable RW 8 Reserved RO 13:9 Reserved RO 15:14 Reserved RO 13.2.37 P_SERR# STATUS REGISTER – OFFSET 68h Bit Function Type Address Parity 16 RWC Error Posted Write 17 ...
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CLKRUN REGISTER – OFFSET 6Ch Bit Function Type Secondary 24 Clock Stop RO Status Secondary 25 CLKRUN RW Enable Primary Clock 26 RW Stop Primary 27 CLKRUN RW Enable CLKRUN 28 RW mode 31:29 Reserved RO 13.2.39 PORT OPTION ...
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Bit Function Type Secondary Memory Read 3 RW Command Alias Enable Secondary Memory Write 4 RW Command Alias Enable Primary Memory Read 5 RW Line/Multiple Alias Enable Secondary Memory Read 6 RW Line/Multiple Alias Enable Primary Memory Write 7 and ...
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Bit Function Type Enable Long 9 RW Request Enable Secondary Hold Request Longer Enable Primary 11 To Hold RW Request Longer 15:12 Reserved RO 13.2.40 CAPABILITY ID REGISTER – OFFSET 80h Bit Function Type Enhanced 7:0 RO ...
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POWER MANAGEMENT DATA REGISTER – OFFSET 84h Bit Function Type 1:0 Power State RW 7:2 Reserved RO 8 PME# Enable RO 12:9 Data Select RO 14:13 Data Scale RO 15 PME status RO 13.2.44 PRIMARY MASTER TIMEOUT COUNTER REGISTER ...
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HOT SWAP CAPABILITY STRUCTURE REGISTER – OFFSET 90h Bit Function Type Device Hide 16 RW Active ENUM# Signal 17 RW Mask 18 Reserved RO 19 LED On/Off RW 21:20 Reserved RO Extraction 22 RWC Status 23 Insertion Status RWC ...
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Bit Function Type 15:9 Reserved RO 14 ELECTRICAL AND TIMING SPECIFICATIONS 14.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AV ...
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AC SPECIFICATIONS Figure 14-1 PCI Signal Timing Measurement Conditions Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal ...
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TIMING Symbol Parameter T SKEW among S_CLKOUT[9:0] SKEW T DELAY between PCLK and S_CLKOUT[9:0] DELAY T P_CLK, S_CLKOUT[9:0] cycle time CYCLE T P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 14.5 33MHZ TIMING Symbol Parameter ...
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... PACKAGE INFORMATION 15.1 128-PIN QFP PACKAGE OUTLINE Figure 15-1 128-pin QFP package outline Thermal characteristics can be found on the web: 15.2 PART NUMBER ORDERING INFORMATION PART NUMBER PI7C8140AMA PI7C8140AMAE 07-0067 2-PORT PCI-TO-PCI BRIDGE http://www.pericom.com/packaging/mechanicals.php SPEED PIN – PACKAGE 66 MHz 128 – QFP 66 MHz 128 – ...