M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet
M95M02-DRMN6TP
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M95M02-DRMN6TP Summary of contents
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... ECOPACK2 (RoHS compliant and Halogen-free) May 2011 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 2 Mbit serial SPI bus EEPROM Doc ID 18203 Rev 4 M95M02-DR Preliminary data SO8N (MN) 150 mils width WLCSP (CS) 1/40 www.st.com 1 ...
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... Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 18203 Rev 4 M95M02-DR ...
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... M95M02-DR 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 Write to Memory Array (WRITE 6.8 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 Read Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10 Lock ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29 8 Power-up and delivery state ...
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... Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 11. DC characteristics Table 12. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 14. M95M02-D WLCSP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/40 Doc ID 18203 Rev 4 M95M02-DR ...
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... Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 20. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 21. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 22. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 36 Figure 23. M95M02-D WLCSP package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 18203 Rev 4 List of figures 5/40 ...
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... They are accessed by an SPI-compatible bus. Their memory array is organized as 262 144 × 8 bits. It can also be seen as 1024 pages of 256 bytes each. The M95M02-DR devices also offer an additional page, named the Identification Page (256 bytes) which can be written and (later) permanently locked in Read-only mode. This ...
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... M95M02-DR Figure 2. SO8N connections 1. See Section 11: Package mechanical data M95xxx HOLD for package dimensions, and how to identify pin-1. Doc ID 18203 Rev 4 Description AI01790D 7/40 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/40 must be held stable and within the specified valid range: CC Table 11). These signals are described next. Doc ID 18203 Rev 4 M95M02- ...
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... M95M02-DR 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. ...
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... S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the t 10/ SPI Memory SPI Memory R Device Device HOLD requirement is met. SHCH Doc ID 18203 Rev 4 M95M02- SPI Memory R Device S W HOLD W HOLD AI12836b ...
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... M95M02-DR 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...
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... CC CC Table 8. (min), V (max)] range defined rises continuously from V CC and the rise time must not vary faster than 1 V/µs. Doc ID 18203 Rev 4 M95M02-DR CC Table 8.). This voltage ). In order to secure a W line with a suitable CC /V package pins reaches a valid and stable V ...
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... M95M02-DR 4.1.4 Power-down During power-down (continuous decrease in the V V operating voltage defined in CC ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...
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... SPI bus. Table 2. Write-protected block size Status Register bits BP1 14/40 Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Doc ID 18203 Rev 4 M95M02-DR for a Array addresses protected none 3 0000h - 3 FFFFh 2 0000h - 3 FFFFh 0 0000h - 3 FFFFh ...
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... M95M02-DR 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Figure 6. High Voltage Control Logic I/O Shift Register Address Register and Counter Doc ID 18203 Rev 4 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only EEPROM area ...
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... Write to Memory Array Writes the page dedicated to identification Reads the lock status of the Identification Page Locks the Identification page in read-only mode 7, to send this instruction to the device, Chip Select (S) is driven low, Doc ID 18203 Rev 4 M95M02-DR Table 3. Table 3), the device automatically Instruction format ...
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... M95M02-DR Figure 7. Write Enable (WREN) sequence 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD Status Register Write Protect 18/40 Table 4) becomes protected against Write Doc ID 18203 Rev 4 M95M02-DR Figure 9. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...
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... M95M02-DR Figure 9. Read Status Register (RDSR) sequence High Impedance Q 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... Hardware write protected The values in the BP1 and (HPM) BP0 bits cannot be changed Table 4. Doc ID 18203 Rev Status Register AI02282D Memory content (1) Protected area Unprotected area Ready to accept Write Protected Write instructions Ready to accept Write Protected Write instructions Table 2. M95M02-DR (1) Table 5. ...
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... M95M02-DR When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven high or low. ...
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... Bits A23 to A18 are Don’t Care. 22/40 11, to send this instruction to the device, Chip Select (S) is first driven Instruction 24-bit address MSB 6, the most significant address bits are Don’t Care. (1) M95M02-DR A17-A0 Doc ID 18203 Rev Data Out MSB M95M02-DR Data Out 2 7 AI13878 ...
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... M95M02-DR 6.6 Read Identification Page The Identification Page (256 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D) ...
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... Instruction 24-bit address High Impedance 6, the most significant address bits are Don’t Care. Doc ID 18203 Rev 4 (as specified in Table 12), at the end of Figure 14, the next byte of (as specified in Table Data byte M95M02-DR 12), at the 39 0 AI13879 ...
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... M95M02-DR Figure 14. Page Write (WRITE) sequence shown in Table Instruction 24-bit address Data byte 2 Data byte the most significant address bits are Don’t Care. Doc ID 18203 Rev Data byte Data byte Instructions AI13880 25/40 ...
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... Table 3), the Chip Select signal (S) is first driven low. The Table 12), at the end of which the Write in Progress (WIP) bit is 15, Chip Select (S) is driven high after the eighth bit of the data byte Doc ID 18203 Rev 4 M95M02-DR Figure 15, the next byte ...
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... M95M02-DR 6.9 Read Lock Status The Read Lock Status instruction (see locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. ...
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... Chip Select (S) being driven high byte boundary (after the eighth bit, b0, of the last data byte that was latched in) ● if the Identification page is locked by the Lock Status bit Figure 17. Lock ID sequence 28/40 Doc ID 18203 Rev 4 M95M02-DR ...
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... ECC (error correction code) and write cycling The M95M02-DR devices offer an ECC (error correction code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC result single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value ...
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... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω) 30/40 Table 7 may cause permanent damage to Parameter (2) Doc ID 18203 Rev 4 M95M02-DR Min. Max. Unit –40 130 °C –65 150 ° ...
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... M95M02- and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... V ≤ V ≤ 5 1.8 V ≤ V < 2 2.5 V ≤ V ≤ 5 1.8 V ≤ V < 2 2.5 V ≤ V ≤ 5 0. –0 –0 – Doc ID 18203 Rev 4 M95M02-DR Min Max Unit 8) ± 2 µA ± 2 µ µA 5 µA 5 µA –0.45 0. –0. 0.4 V 0.8 V ...
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... M95M02-DR Table 12. AC characteristics Symbol SLCH t t SHCH t SHSL t CHSH t CHSL ( ( (2) t CLCH (2) t CHCL t DVCH t CHDX t HHCH t HLCH t CLHL t CLHH (2) t SHQZ (3) t CLQV t CLQX (2) t QLQH (2) t QHQL t HHQV (2) t HLQZ must never be less than the shortest possible clock period ...
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... DC and AC parameters Figure 19. Serial input timing S tCHSL C tDVCH D Q Figure 20. Hold timing HOLD 34/40 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 18203 Rev 4 M95M02-DR tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...
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... M95M02-DR Figure 21. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 18203 Rev 4 DC and AC parameters tSHSL tSHQZ AI01449f 35/40 ...
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... Doc ID 18203 Rev 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.0110 0.0067 0.1929 0.1890 0.2362 0.2283 0.1535 0.1496 0.0500 - 0.0098 0° 0.0157 0.0409 M95M02-DR ® Max 0.0689 0.0098 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 - 0.0197 8° 0.0500 ...
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... M95M02-DR Figure 23. M95M02-D WLCSP package outline Table 14. M95M02-D WLCSP package mechanical data Symbol (ball diam Values in inches are converted from mm and rounded to 4 decimal digits. millimeters Typ Min Max 0.295 0.265 0.325 0.225 0.210 0.240 0.090 0.065 0.115 3.556 3.536 3.576 2 ...
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... T = tape and reel packing Plating technology ECOPACK2 For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 38/40 M95M02-D ® (RoHS compliant and Halogen-free) Doc ID 18203 Rev 4 M95M02- ...
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... M95M02-DR 13 Revision history Table 16. Document revision history Date Revision 15-Nov-2010 10-Dec-2010 10-Jan-2011 10-May-2011 1 Initial release. Updated DC and AC characteristics according to characterization test 2 results. 3 Updated ordering information. Updated Table 12: AC characteristics 4 characteristics. Doc ID 18203 Rev 4 Revision history Changes and related text, and Table 11: DC ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 40/40 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 18203 Rev 4 M95M02-DR ...