BR24L02NUX-WTR Rohm Semiconductor, BR24L02NUX-WTR Datasheet

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BR24L02NUX-WTR

Manufacturer Part Number
BR24L02NUX-WTR
Description
IC EEPROM 2KBIT 100KHZ VSON8
Manufacturer
Rohm Semiconductor
Series
-r
Datasheet

Specifications of BR24L02NUX-WTR

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
BR24L02NUX-WTR
Manufacturer:
ROHM
Quantity:
50 000
Part Number:
BR24L02NUX-WTR
Manufacturer:
ROHM/罗姆
Quantity:
20 000
Serial EEPROM Series
High Reliability Series
EEPROMs I
© 2009 ROHM Co., Ltd. All rights reserved.
www.rohm.com
BR24L□□-W Series,BR24S□□□-W Series
a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
and assort 8Kbit~256Kbit.
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides
BR24L□□-W Series assort 1Kbit~64Kbit. BR24S□□□-W Series are possible to operate at high speed in low voltage
BR24L□□-W Series
BR24S□□□-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
BR24S08-W, BR24S16-W, BR24S32-W, BR24S64-W,
BR24S128-W, BR24S256-W
2
C BUS
Contents
1/40
・・・・P2
・・・P20
2009.09 - Rev.D
No.09001EDT04

Related parts for BR24L02NUX-WTR

BR24L02NUX-WTR Summary of contents

Page 1

Serial EEPROM Series High Reliability Series 2 EEPROMs I C BUS BR24L□□-W Series,BR24S□□□-W Series ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while ...

Page 2

BR24L□□-W Series,BR24S□□□-W Series Serial EEPROM Series High Reliability Series 2 EEPROMs I C BUS BR24L□□-W Series ●Description BR24L□□-W series is a serial EEPROM of I ●Features 1) Completely conforming to the world standard I 2) Other devices than EEPROM can ...

Page 3

... Permissible dissipation Storage temperature range Action temperature range Terminal voltage When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,* reduced per 1℃ ●Memory cell characteristics (Ta=25℃, Vcc=1.8~5.5V) Parameter *2 Number of data rewrite times *2 Data hold years ○Shipment data all address FFh *1 BR24L02/16/32 ...

Page 4

BR24L□□-W Series,BR24S□□□-W Series ●Action timing characteristics (Unless otherwise specified, Ta= Parameter SCL frequency Data clock “HIGH“ time Data clock “LOW“ time *2 SDA, SCL rise time *2 SDA, SCL fall time Start condition hold time Start condition setup time Input ...

Page 5

BR24L□□-W Series,BR24S□□□-W Series ●Sync data input / output timing tR tF tHIGH SCL tSU:DAT tLOW tHD:STA SDA (入力) (input) tPD tBUF SDA (output) (出力) ○Input read at the rise edge of SCL ○Data output in sync with the fall of ...

Page 6

BR24L□□-W Series,BR24S□□□-W Series ●Block diagram * 7bit 8bit 9bit 10bi *2 Address A1 2 decoder * High voltage GND 4 generating circuit * 1 7bit : BR24L01A-W 8bit : BR24L02-W 9bit : BR24L04-W ●Pin assignment and ...

Page 7

BR24L□□-W Series,BR24S□□□-W Series ●Characteristic data (The following values are Typ. ones SPEC 3 2 Ta=85℃ Ta=-40℃ Ta=25℃ Vcc[V] Fig.3 H input voltage VIH1,2 1 0.8 0.6 Ta=25℃ Ta=85℃ ...

Page 8

BR24L□□-W Series,BR24S□□□-W Series ●Characteristic data (The following values are Typ. ones). 50 SPEC1,2 0 Ta=-40℃ Ta=25℃ -50 Ta=85℃ -100 -150 -200 Vcc[V] Fig.21 Input data hold time tHD:DAT(HIGH) 300 SPEC2 200 SPEC1 100 Ta=85℃ ...

Page 9

BR24L□□-W Series,BR24S□□□-W Series 2 C BUS communication ●I 2 ○I C BUS data communication BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always ...

Page 10

... Fig.39 Page write cycle (BR24L32/64-W) ・Data is written to the address designated by word address (n-th address) ・By issuing stop bit after 8bit data input, write to memory cell inside starts. ・When internal write is started, command is not accepted for tWR (5ms at maximum). ・By page write cycle, the following can be written in bulk : bytes ( BR24L01A-W, BR24L02-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to " ...

Page 11

BR24L□□-W Series,BR24S□□□-W Series ○Notes on write cycle continuous input SLAVE WORD R T ADDRESS ADDRESS(n) SDA *1 LINE Note ...

Page 12

BR24L□□-W Series,BR24S□□□-W Series ○Internal address increment Page write mode (in the case of BR24L02-W) WA7 ----- WA4 WA3 0 ----- ----- ----- ----- 0 0 06h 0 ----- ...

Page 13

BR24L□□-W Series,BR24S□□□-W Series ●Read Command ○Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. ...

Page 14

BR24L□□-W Series,BR24S□□□-W Series ●Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to ...

Page 15

BR24L□□-W Series,BR24S□□□-W Series ●WP valid timing (write cancel usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, ...

Page 16

BR24L□□-W Series,BR24S□□□-W Series ●I/O peripheral circuit ○Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R this resistance value from microcontroller V limited. The smaller the R , ...

Page 17

BR24L□□-W Series,BR24S□□□-W Series ●Cautions on microcontroller connection ○ BUS recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a ...

Page 18

BR24L□□-W Series,BR24S□□□-W Series 2 C BUS input / output circuit ●I ○Input (A0,A2,SCL) Fig.57 Input pin circuit diagram ○Input / output (SDA) Fig.58 Input / output pin circuit diagram ○Input (A1, WP) Fig.59 Input pin circuit diagram ●Notes on power ...

Page 19

BR24L□□-W Series,BR24S□□□-W Series 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures the case when the above condition 1 cannot be observed. ...

Page 20

BR24L□□-W Series,BR24S□□□-W Series Serial EEPROM Series High Reliability Series 2 EEPROMs I C BUS BR24S□□□-W Series ●Description BR24S□□□-W series is a serial EEPROM of I2C BUS interface method. ●Features 1) Completely conforming to the world standard I and serial data ...

Page 21

... Impressed voltage Permissible dissipation Storage temperature range Action temperature range Terminal voltage *When using at Ta=25℃ or higher, 4.5mW(*1,*2), 3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,* reduced per 1℃ ●Memory cell characteristics (Ta=25℃, Vcc=1.7~5.5V) Parameter *1 Number of data rewrite times *1 Data hold years *1 Not 100% TESTED ● ...

Page 22

BR24L□□-W Series,BR24S□□□-W Series ●Action timing characteristics (Unless otherwise specified, T=-40~+85℃, Vcc=1.7~5.5V) Parameter SCL Frequency Data clock "High" time Data clock "Low" time SDA, SCL rise time *1 SDA, SCL fall time *1 Start condition hold time Start condition setup time ...

Page 23

BR24L□□-W Series,BR24S□□□-W Series ●Sync data input/output timing tR tF tHIGH SCL tSU:DAT tLOW tHD:STA SDA (Input) (入力) tBUF tPD SDA (Output) (出力) ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Fig.1-(a) ...

Page 24

BR24L□□-W Series,BR24S□□□-W Series ●Pin assignment and description Terminal Input/ name Output A0 Input A1 Input A2 Input GND - SDA Input / Output SCL Input WP Input Vcc - ●Characteristic data (The following values are Typ. ones.) 6 Ta=-40℃ 5 ...

Page 25

BR24L□□-W Series,BR24S□□□-W Series ●Characteristic data (The following values are Typ. ones.) 2.5 SPEC 2 1.5 Ta=-40℃ Ta=25℃ 1 Ta=85℃ 0 SUPPLY VOLTAGE : Vcc[V] Fig.9 Current consumption at WRITE operation I (f ...

Page 26

BR24L□□-W Series,BR24S□□□-W Series ●Characteristic data (The following values are Typ. ones.) 5 Ta=-40℃ 4 Ta=25℃ Ta=85℃ SPEC SUPPLY VOLTAGE : Vcc[V] Fig.24 BUS open time before transmission t BUF 0.6 ...

Page 27

BR24L□□-W Series,BR24S□□□-W Series 2 C BUS communication ●I 2 ○I C BUS data communication BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always ...

Page 28

... Fig.36 Page write cycle (BR24S32/64/128/256-W) ・Data is written to the address designated by word address (n-th address). ・By issuing stop bit after 8bit data input, write to memory cell inside starts. ・When internal write is started, command is not accepted for tWR (5ms at maximum). ・By page write cycle, the following can be written in bulk bytes (BR24S08-W, BR24S16-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to " ...

Page 29

BR24L□□-W Series,BR24S□□□-W Series ○Notes on write cycle continuous input SLAVE WORD R T ADDRESS ADDRESS(n) SDA LINE note ...

Page 30

BR24L□□-W Series,BR24S□□□-W Series ○Internal address increment Page write mode (in the case of BR24S16-W) WA7 ----- WA4 WA3 0 ----- ----- ----- ----- 0 1 0Eh 0 ----- ...

Page 31

BR24L□□-W Series,BR24S□□□-W Series ●Read Command ○Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. ...

Page 32

BR24L□□-W Series,BR24S□□□-W Series ●Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kids of them are shown in the figure below. (Refer to ...

Page 33

BR24L□□-W Series,BR24S□□□-W Series ●WP valid timing (write cancel usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, ...

Page 34

BR24L□□-W Series,BR24S□□□-W Series ●I/O peripheral circuit ○Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R this resistance value from microcontroller V limited. The smaller the R , ...

Page 35

BR24L□□-W Series,BR24S□□□-W Series ●Cautions on microcontroller connection ○ BUS recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a ...

Page 36

BR24L□□-W Series,BR24S□□□-W Series 2 C BUS input / output circuit ●I ○Input (A0, A1, A2, SCL, WP) Fig.54 Input pin circuit diagram ○Input/Output (SDA) Fig.55 Input /output pin circuit diagram ●Notes on power ON At power on internal ...

Page 37

BR24L□□-W Series,BR24S□□□-W Series ●Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. ●Vcc noise countermeasures ○Bypass capacitor When noise or ...

Page 38

BR24L□□-W Series,BR24S□□□-W Series ●Ordering part number Part No. BUS type Operating 2 temperature/ 24 : Power source voltage L: -40 ℃ ~+85 ℃ -40 ℃ ~+85 ℃ / ●Package specifications SOP8 5.0±0.2 ...

Page 39

BR24L□□-W Series,BR24S□□□-W Series SSOP-B8 3.0 ± 0.2 (MAX 3.35 include BURR 0.15 ± 0.1 S 0.1 +0.06 0.22 -0.04 0.08 (0.52) 0.65 TSSOP-B8 3.0 ± 0.1 (MAX 3.35 include BURR) 4 ± ...

Page 40

BR24L□□-W Series,BR24S□□□-W Series MSOP8 2.9±0.1 (MAX 3.25 include BURR) + 6° 4° −4° 1PIN MARK 0.145 0.475 S +0.05 0.22 –0.04 0.08 S 0.65 VSON008X2030 2.0±0.1 1PIN MARK S 0.08 S 1.5±0.1 ...

Page 41

No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose ...

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