MT47H256M8THN-25E:H Micron Technology Inc, MT47H256M8THN-25E:H Datasheet
MT47H256M8THN-25E:H
Specifications of MT47H256M8THN-25E:H
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MT47H256M8THN-25E:H Summary of contents
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TwinDie™ DDR2 SDRAM MT47H512M4 – 32 Meg Banks x 2 Ranks MT47H256M8 – 16 Meg Banks x 2 Ranks For the latest component data sheet, refer to Micron’s Web site: Functionality The ...
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Ball Assignments and Descriptions Figure 1: 63-Ball FBGA Assignments – x4, x8 (Top View NF, NU/RDQS NF, DQ6 DQ1 DDQ D NF, DQ4 DDL F CKE0 G BA2 ...
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... Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a precharge command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2:0]) or all device banks (A10 HIGH) ...
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... Functional Description The 2Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access memory device that contains 2,147,483,648 bits and is internally configured as two 8-bank 1Gb DDR2 SDRAM devices. Although each die is tested individually within the dual-die package, some TwinDie test results may vary from a like die tested within a monolithic die package. ...
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Functional Block Diagrams Figure 2: Functional Block Diagram (32 Meg Banks x 2 Ranks) CS1# RAS# CKE1 CAS# ODT1 WE# Figure 3: Functional Block Diagram (16 Meg Banks x 2 Ranks) CS1# ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the devices at these or any other condi- tions outside those indicated in the device data ...
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Table 5: Temperature Limits Symbol Parameter T Storage temperature STG T Operating temperature – commercial C Notes: 1. Maximum storage case temperature; T shown in Figure 4. This case temperature limit is allowed to be exceeded briefly during package reflow, ...
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I Specifications and Conditions CDD Table 7: DDR2 I Specifications and Conditions CDD Notes: 1–8 apply to the entire document; notes appear on page 9 Parameter/Condition Operating one bank active-precharge current ...
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Table 7: DDR2 I Specifications and Conditions (continued) CDD Notes: 1–8 apply to the entire document; notes appear on page 9 Parameter/Condition Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are ...
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Package Dimensions Figure 5: 63-Ball FBGA Package Dimensions (Part Rev. H) Seating plane A 0.12 A 63X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post reflow on Ø0.33 ...