SC4525DSETRT Semtech, SC4525DSETRT Datasheet - Page 11

• Manufacturer Part Number: SC4525DSETRT
• Description: IC BUCK ADJ 3A 8SOIC
• Manufacturer: Semtech
• Series: -r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of SC4525DSETRT

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1 V ~ 16.74 V
• Current - Output: 3A
• Frequency - Switching: 65kHz ~ 350kHz
• Voltage - Input: 3 V ~ 18 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SC4525DSETR

© 2011 Semtech Corp.
Applications Information (Cont.)
switching frequency. The measured minimum off time is
100ns typically. If the required duty cycle is higher than
the attainable maximum, then the output voltage will not
be able to reach its set value in continuous-conduction
mode.
Inductor Selection
The inductor ripple current for a non-synchronous step-
down converter in continuous-conduction mode is
where F
the inductance.
An inductor ripple current between 20% to 50% of the
maximum load current, I
among efficiency, cost and size. Re-arranging Equation (3)
and assuming 35% inductor ripple current, the inductor is
given by
If the input voltage varies over a wide range, then choose
L
converter operation at the input voltage extremes.
The peak current limit of SC4525D power transistor is at
least 3.9A. The maximum deliverable load current for the
SC4525D is 3.9A minus one half of the inductor ripple
current.
Input Decoupling Capacitor
The input capacitor should be chosen to handle the RMS
ripple current of a buck converter. This value is given by
The input capacitance must also be high enough to keep
input ripple voltage within specification. This is important
in reducing the conductive EMI from the regulator. The
input capacitance can be estimated from
1
based on the nominal input voltage. Always verify
R
R
R
R
R
R
D
D
L
L
I
I
D
D
R
R
D
D
C
C
D
D
L
L
I
I
C
C
D
D
D
D
RMS
RMS
D
D
D
D
L
L
I
I
D
D
C
C
D
D
L
L
I
I
D
D
D
D
C
C
4
4
RMS
RMS
RMS
RMS
RMS
RMS
4
4
1
1
4
4
1
1
I
I
4
4
V
V
IN
IN
1
1
I
I
V
V
1
1
=
=
IN
IN
I
I
V
V
L
L
IN
IN
I
I
V
V
IN
IN
=
=
L
L
SW
=
=
=
=
=
=
L
L
L
L
O
O
=
=
=
=
=
=
O
O
O
O
=
=
=
=
=
=
O
O
=
=
=
=
_
_
>
>
=
=
V
V
_
_
>
>
=
=
_
_
>
>
R
R
=
=
_
_
>
>
V
V
V
V
R
R
=
=
R
R
V
V
CIN
CIN
R
R
=
=
is the switching frequency (350kHz) and L
V (
V (
=
=
IN
IN
CIN
CIN
V (
V (
CIN
CIN
=
=
V (
V (
CIN
CIN
IN
IN
V (
V (
6
6
V (
V (
IN
IN
IN
IN
4
4
6
6
V (
V (
4
4
6
6
V (
V (
4
4
6
6
V (
V (
D
D
4
4
D
D






D
D
O
O
35
35
D
D
O
O
20
20
+
+






O
O
20
20






20
20
+
+






O
O
D ⋅
D ⋅
+
+
O
O
+
+
=
=
I
I
D ⋅
D ⋅
O
O
1
1
V
V
D ⋅
D ⋅
=
=
I
I
O
O
=
=
D ⋅
D ⋅
O
O
I
I
1
1
V
V
L
L
=
=
I
I
1
1
V
V
+
+
1
1
L
L
V
V
+
+
L
L
V
V
+
+
L
L
+
+
O
O
V
V
V
V
V
V
O
O
0 .
0 .
+
+
I
I
V
V
O
O
V
V
0 .
0 .
+
+
I
I
%
%
%
%
V
V
0 .
0 .
O
O
⋅
⋅
+
+
I
I
D
D
V
V
%
%
V
V
F
F
0 .
0 .
O
O
+
+
%
%
I
I
⋅
⋅
V
V
⋅
⋅
D
D
O
O
V
V
O
O
F
F
V
V
D
D
O
O
⋅
⋅
V
V
D
D
F
F
V
V
I
I
O
O
V
V
O
O
+
+


F
F
 
 


O
O
V
V
I
I
+
+
O
O


 
 


IN
IN
I
I
V
V
SW
SW
+
+
O
O


 
 


I
I
V
V
+
+
IN
IN


 
 


O
O
IN
IN
V
V
SW
SW
D
D
−
−
⋅
⋅
D
D
IN
IN
O
O
V
V
⋅
⋅
D
D
⋅
⋅
ESR
ESR
V
V
SW
SW
−
−
V
V
V
V
SW
SW
D
D
⋅
⋅
O
O
⋅
⋅
V
V
ESR
ESR
−
−
⋅
⋅
⋅
⋅
ESR
ESR
−
−
⋅
⋅
D
D
ESR
ESR
V
V
I
I
I
I
I
I
V
V
D
D
)
)
D
D
I
I
)
)
V
V
)
)
O
O
D
D
)
)
⋅
⋅
O
O
V
V
O
O
−
−
V
V
O
O
⋅
⋅
⋅
⋅
D
D
−
−
V
V
⋅
⋅
)
)
⋅
⋅
−
−
V
V
⋅
⋅
D
D
)
)
−
−
V
V
D
D
F
F
⋅
⋅
⋅
⋅
D
D
)
)
⋅
⋅
D
D
F
F
⋅
⋅
D
D
)
)
F
F
1 (
1 (
⋅
⋅
CESAT
CESAT
⋅
⋅
D
D
F
F
1 (
1 (
⋅
⋅
CESAT
CESAT
⋅
⋅
⋅
⋅
D
D
1
1
L
L
⋅
⋅
CESAT
CESAT
1 (
1 (
⋅
⋅
1 (
1 (
⋅
⋅
CESAT
CESAT
⋅
⋅
SW
SW
1
1
L
L
F
F
1
1
SW
SW
⋅
⋅
L
L
F
F
1
1
L
L
F
F
SW
SW
1 (
1 (
F
F
SW
SW
⋅
⋅
1 (
1 (
1 (
1 (
1
1
+
+
⋅
⋅
1 (
1 (






1
1
SW
SW
+
+
⋅
⋅
1
1
SW
SW
⋅
⋅
+
+
SW
SW








SW
SW




1 (
1 (
1
1
+
+
−
−
−
−






1 (
1 (
−
−
−
−
1 (
1 (
1 (
1 (
−
−
8
8
−
−
) D
) D
8
8
−
−
) D
) D
8
8
−
−
) D
) D
8
8
) D
) D
−
−
−
−
) D
) D
−
−
⋅
⋅
−
−
) D
) D
O
) D
) D
⋅
⋅
) D
) D
⋅
⋅
⋅
⋅
F
F
, gives a good compromise
) D
) D
F
F
) D
) D
F
F
) D
) D
F
F
) D
) D
SW
SW
SW
SW
SW
SW
1
1
SW
SW
1
1
1
1
1
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O


 
 




 
 




 
 




 
 


(3)
(4)
(5)
(6)
1
is
R
R
C
C
C
C
G
G
R
R
C
C
C
C
A
A
A
A
R
R
R
R
C
C
C
C
G
G
V
V
V
V
C
C
R
R
C
C
R
R
A
A
A
A
C
C
C
C
G
G
C
C
V
V
V
V
A
A
A
A
R
R
C
C
C
C
G
G
R
R
C
C
C
C
A
A
A
A
V
V
V
V
V
V
V
V
where DV
Multi-layer ceramic capacitors, which have very low ESR (a
few mW) and can easily handle high RMS ripple current, are
the ideal choice for input filtering. A single 4.7µF to 10µF
X5R ceramic capacitor is adequate for most applications.
For high voltage applications, a small ceramic (1µF or
2.2µF) can be placed in parallel with a low ESR electrolytic
capacitor to satisfy both the ESR and bulk capacitance
requirements.
Output Capacitor
The output ripple voltage DV
expressed as
7
7
where C
Since the inductor ripple current DI
decreases (Equation (3)), the output ripple voltage is
therefore the highest when V
A 22µF to 47µF X5R ceramic capacitor is found adequate
o
o
for output filtering in most applications. Ripple current
in the output capacitor is not a concern because the
inductor current of a buck converter directly feeds C
resulting in very low ripple current. Avoid using Z5U
PWM
PWM
and Y5V ceramic capacitors for output filtering because
these types of capacitors have high temperature and high
voltage coefficients.
7
7
Freewheeling Diode
Use of Schottky barrier diodes as freewheeling rectifiers
reduces diode reverse recovery input current spikes,
easing high-side current sensing in the SC4525D. These
diodes should have an average forward current rating
at least 3A and a reverse blocking voltage of at least a
few volts higher than the input voltage. For switching
regulators operating at low duty cycles (i.e. low output
voltage to input voltage conversion ratios), it is beneficial
to use freewheeling diodes with somewhat higher
average current ratings (thus lower forward voltages). This
C
C
C
C
5
5
8
8
c
c
5
5
8
8
7
7
o
o
c
c
PWM
PWM
7
7
7
7
C
C
C
C
5
5
8
8
5
5
7
7
8
8
o
o
c
c
PWM
PWM
C
C
C
C
7
7
5
5
8
8
o
o
PWM
PWM
7
7
5
5
C
C
C
C
5
5
8
8
c
c
5
5
8
8
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
10
10
. 0
. 0
1 (
1 (
2
2
2
2
−
−
−
−
2
2
10
10
2
2
10
10
. 0
. 0
1 (
1 (
≈
≈
. 0
. 0
1 (
1 (
−
−
−
−
2
2
2
2
2
2
2
2
10
10
≈
≈
−
−
−
−
. 0
. 0
2
2
2
2
1 (
1 (
2
2
2
2
2
2
≈
≈
2
2
2
2
−
−
−
−
g
g
≈
≈
g
g
⋅ π
⋅ π
g
g
g
g
⋅ π
⋅ π
⋅ π
⋅ π
π
π
π
π
R
R
20
20
20
20
28
28
⋅ π
⋅ π
20
20
20
20
28
28
⋅ π
⋅ π
π
π
⋅ π
⋅ π
π
π
π
π
20
20
20
20
+
+
28
28
G
G
m
m
⋅ π
⋅ π
D
D
L
L
I
I
⋅ π
⋅ π
π
π
π
π
D
D
10
10
D
D
20
20
G
G
C
C
20
20
28
28
+
+
m
m
G
G
+
+
G
G
m
m
10
10
RMS
RMS
10
10
A
A
20
20
+
+
F
F
m
m
F
F
A
A
10
10
4
4
20
20
F
F
F
F
A
A
F
F
20
20
1
1
C
C
A
A
20
20
F
F
F
F
CA
CA
C
C
1
1
1
1
I
I
V
V
16
16
600
600
IN
IN
C
C
O
CA
CA
/ s
/ s
1
1
1
1
1 Z
1 Z
P
P
16
16
600
600
C
C
CA
CA
1
1
=
=
/ s
/ s
P
P
16
16
600
600
CA
CA
L
L
1 Z
1 Z
/ s
/ s
1
1
1
1
1 Z
1 Z
16
16
600
600
/ s
/ s
1 Z
1 Z
P
P
1
1
=
=
⋅
⋅
⋅
⋅
⋅
⋅
R
R
O
O
=
=
1
1
⋅
⋅
⋅
⋅
⋅
⋅
R
R
⋅
⋅
⋅
⋅
IN
15
15
is the output capacitance.
⋅
⋅
R
R
1
1
⋅
⋅
⋅
⋅
⋅
⋅
R
R
15
15
log
log
log
log
10
10
15
15
20
20
⋅
⋅
log
log
log
log
=
=
10
10
_
_
>
>
15
15
20
20
log
log
⋅
⋅
log
log
10
10
R
R
R
R
V
V
log
log
log
log
10
10
20
20
⋅
⋅
R
R
G
G
20
20
⋅
⋅
R
R
R
R
R
R
9 .
9 .
ω
ω
R
R
G
G
=
=
R
R
R
R
9 .
9 .
CIN
CIN
⋅
⋅
R
R
G
G
is the allowable input ripple voltage.
V (
V (
ω
ω
9 .
9 .
G
G
R
R
⋅
⋅
9 .
9 .
ω
ω
R
R
IN
IN
⋅
⋅
ω
ω
⋅
⋅
7
7
10
10
7
7
6
6
V (
V (
10
10
4
4
PWM
PWM
7
7
7
7
S
S
10
10
7
7
PWM
PWM
⋅
⋅
p
p
7
7
S
S
10
10
PWM
PWM
7
7
D
D
PWM
PWM
S
S


 
 








⋅
⋅
−
−
p
p
p
p
⋅
⋅
S
S
20
20
⋅
⋅
p
p








 
 








−
−
O
O


 
 
10
10








−
−
+
+


 
 








1 ( )
1 ( )
−
−
10
10
3
3
,
,
10
10
1 ( )
1 ( )
D ⋅
D ⋅
10
10
O
O
3
3
,
,
1 ( )
1 ( )
G
G
=
=
28
28
I
I
3
3
1 ( )
1 ( )
,
,
1
1
V
V
3
3
,
,
G
G
28
28
G
G
28
28
L
L
+
+
3
3
G
G
28
28
1
1
3
3
V
V
1
1
3
3
3
3
1
1
O
O
=
=
1 (
1 (
V
V
CA
CA
1
1
1
1
0 .
0 .
+
+
%
%
I
I
1 (
1 (
=
=
1 (
1 (
CA
CA
1
1
=
=
⋅
⋅
3
3
CA
CA
=
=
1
1
1 (
1 (
D
D
O
O
⋅
⋅
CA
CA
V
V
1
1
F
F
1
1
3
3
V
V
+
+
3
3
1
1
⋅
⋅
O
O
+
+
1
1
⋅
⋅
3
3
I
I
⋅
⋅
+
+
+
+


 
 


1
1
+
+
⋅
⋅
22
22
22
22
IN
IN
R
R
⋅
⋅
V
V
SW
SW
22
22
D
D
22
22
O
O
V
V
R
R
⋅
⋅
⋅
⋅
⋅
⋅
22
22
22
22
R
R
⋅
⋅
+
+
−
−
⋅
⋅
22
22
22
22
6
6
⋅
⋅
ESR
ESR
R
R
+
+
/ s
/ s
⋅
⋅
+
+
⋅
⋅
6
6
I
I
+
+
/ s
/ s
22
22
6
6
/ s
/ s
D
D
)
)
6
6
V
V
/ s
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