SC4525DSETRT Semtech, SC4525DSETRT Datasheet - Page 13

• Manufacturer Part Number: SC4525DSETRT
• Description: IC BUCK ADJ 3A 8SOIC
• Manufacturer: Semtech
• Series: -r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of SC4525DSETRT

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1 V ~ 16.74 V
• Current - Output: 3A
• Frequency - Switching: 65kHz ~ 350kHz
• Voltage - Input: 3 V ~ 18 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SC4525DSETR

D
D
C
C
O
O
20
20
D ⋅
D ⋅
O
O
=
=
I
I
O
O
L
L
+
+
+
+
I
I
%
%


 
 


⋅
⋅
V
V
O
O
F
F
V
V
I
I


 
 


© 2011 Semtech Corp.
Applications Information (Cont.)
Loop Compensation
The goal of compensation is to shape the frequency
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability.
The block diagram in Figure 7 shows the control loops of a
buck converter with the SC4525D. The inner loop (current
loop) consists of a current sensing resistor (R
and a current amplifier (CA) with gain (G
outer loop (voltage loop) consists of an error amplifier
IN
IN
(EA), a PWM modulator, and a LC filter.
Since the current loop is internally closed, the remaining
task for the loop compensation is to design the voltage
compensator (C
For a converter with switching frequency F
inductance L
control (V
given by:
This transfer function has a finite DC gain
an ESR zero F
D
D
O
O
V
V
SW
SW
⋅
⋅
⋅
⋅
ESR
ESR
I
I
D
D
)
)
O
O
⋅
⋅
⋅
⋅
)
)
F
F
⋅
⋅
D
D
1 (
1 (
⋅
⋅
⋅
⋅
FB
FB
L
L
F
F
SW
SW
1 (
1 (
⋅
⋅
1
1
SW
SW
+
+
−
−
1 (
1 (
R
R
R
R
R
R
C
C
C
C
C
C
C
C
G
G
G
G
R
R
C =
C =
C =
C =
A
A
A
A
A
A
A
A
V
V
V
V
V
V
V
V
REF
REF
−
−
) D
) D
8
8
7
7
7
7
7
7
o
o
o
o
c
c
c
c
PWM
PWM
PWM
PWM
7
7
C
C
C
C
C
C
C
C
Figure 7. Block diagram of control loops
5
5
5
5
8
8
8
8
5
5
5
5
−
−
) D
) D
⋅
⋅
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
C
F
F
+
+
) D
) D
-
-
CONTROLLER AND SCHOTTKY DIODE
CONTROLLER AND SCHOTTKY DIODE
) to output (V
10
10
SW
SW
. 0
. 0
1 (
1 (
10
10
. 0
. 0
1 (
1 (
−
−
−
−
−
−
−
−
2
2
2
2
2
2
2
2
≈
≈
≈
≈
1
1
g
g
EA
EA
g
g
⋅ π
⋅ π
1
⋅ π
⋅ π
Z
20
20
20
20
28
28
⋅ π
⋅ π
⋅ π
⋅ π
20
20
20
20
28
28
C5
C5
R7
R7
, output capacitance C
G
G
G
G
+
+
+
+
m
m
m
m
10
10
⋅
⋅
10
10
at
A
A
A
A
20
20
20
20
C
C
C
C
C
C
CA
CA
CA
CA
1
1
1
1
16
16
16
16
600
600
600
600
/ s
/ s
/ s
/ s
5
, R
⋅
⋅
⋅
⋅
O
O
⋅
⋅
COMP
COMP
⋅
⋅
⋅
⋅
⋅
⋅
R
R
R
R
15
15
15
15
log
log
log
log
log
log
log
log
10
10
10
10
20
20
20
20
⋅
⋅
⋅
⋅
G
G
G
G


 
 


Vramp
Vramp
9 .
9 .
9 .
9 .
R
R
R
R
ω
ω
ω
ω
7
Vc
Vc
⋅
⋅
⋅
⋅
, and C
10
10
10
10
PWM
PWM
PWM
PWM
S
S
p
p
S
S
⋅
⋅
⋅
⋅
p
p


 
 








−
−


 
 








−
−
10
10
10
10
1 ( )
1 ( )
1 ( )
1 ( )
3
3
3
3
,
,
,
,
G
G
28
28
G
G
28
28
G
G
R
R
C8
C8
C
C
C
C
CA
CA
3
3
3
3
V
V
V
V
1
1
MODULATOR
MODULATOR
1
1
1 (
1 (
=
=
=
=
1 (
1 (
CA
CA
CA
CA
1
1
1
1
7
7
o
o
c
c
PWM
PWM
5
5
3
3
8
8
8
8
3
3
1
1
1
1
⋅
⋅
⋅
⋅
O
+
+
+
+
PWM
PWM
⋅
⋅
⋅
⋅
22
22
22
22
22
22
22
22
R
R
) transfer function in Figure 7 is
=
=
R
R
=
=
⋅
⋅
⋅
⋅
+
+
=
=
=
=
+
+
6
6
6
6
/ s
/ s
8
/ s
/ s
22
22
22
22
).
S
S
S
S
10
10
1 .
1 .
1 (
1 (
1 .
1 .
R s
R s
R s
R s
2
2
2
2
2
2
≈
≈
Rs
Rs
.
.
1 .
1 .
1
1
1
1
.
.
1 .
1 .
g
g
k 3
k 3
k 3
k 3
⋅
⋅
⋅
⋅
ω
ω
ω
ω
π
π
1 .
1 .
1 .
1 .
⋅ π
⋅ π
π
π
2
2
⋅
⋅
+
+
G
G
m
m
2
2
⋅
⋅
ESR
ESR
ESR
ESR
⋅
⋅
⋅
⋅
A
A
20
20
F
F
n
n
n
n
F
F
10
10
10
10
ω
ω
ω
ω
10
10
C
C
π
π
π
π
10
10
CA
CA
1
1
1
1
Io
Io
600
600
Q
Q
Q
Q
/ s
/ s
1 Z
1 Z
P
P
⋅
⋅
⋅
⋅
F
F
p
p
p
p
1
1
F
F
10
10
10
10
R
R
C
C
C
C
1
1
1
1
+
+
+
+
C
C
C
C
−
−
⋅
⋅
−
−
R
R
R
R
≈
≈
≈
≈
3
3
3
3
G
G
O
O
O
O
R
R
3
3
3
3
ω
ω
C
C
C
C
s
s
SW
SW
s
s
)
)
7
7
7
7
3
3
3
3
)
)
PWM
PWM
R
R
S
S
R
R
p
p
=
=
=
=
⋅
⋅
O
O
O
O
O
⋅
⋅
⋅
⋅
2
2
2
2
10
10
1 ( )
1 ( )
1
1
1
1
C
C
C
C
,
,
2
2
=
=
2
2
=
=
. 0
. 0
. 0
. 0
and loading R, the
/
/
/
/
⋅
⋅
⋅
⋅
O
O
⋅ π
⋅ π
O
O
⋅ π
⋅ π
12
12
12
12
1 (
1 (
ω
ω
ω
ω
V
V
V
V
V
V
V
V
45
45
45
45
3
3
+
+
,
,
,
,
FB
FB
FB
FB
O
O
2
2
2
2
n
n
n
n
O
O
Fig.8: Bode plot of loop gains
Fig.8: Bode plot of loop gains
L1
L1
⋅
⋅
80
80
+
+
80
80
R
R
pF
pF
pF
pF
C
C
C
C
G
G
C
C
C
C
/ s
/ s
)
)
)
)
V
V
V
V
22
22
nF
nF
nF
nF
Co
Co
Resr
Resr




 
 
 
 




CA
o
o
c
c
PWM
PWM
7
7
5
5
R s
R s
8
8
5
5
8
8
⋅
⋅
⋅
⋅
ω
ω
=
=
=
=
=18.5). The
=
=
=
=
=
=
=
=
1 .
1 .
10
10
s
10
10
ESR
ESR
SW
=3.53mW)
n
n
(8)
ω
ω
10
10
1 (
1 (
2
2
2
2
2
2
2
2
≈
≈
Q
Q
⋅
⋅
, output
1
1
g
g
1
1
p
p
10
10
⋅ π
⋅ π
3
3
3
3
C
C
π
π
⋅ π
⋅ π
π
π
G
G
+
+
+
+
m
m
≈
≈
A
A
20
20
F
F
F
F
⋅
⋅
⋅
⋅
ω
ω
ω
ω
O
O
C
C
Vo
Vo
CA
CA
1
1
1
1
16
16
600
600
22
22
22
22
s
s
/ s
/ s
1 Z
1 Z
P
P
3
3
)
)
R4
R4
R6
R6
Z
Z
Z
Z
R
R
1
1
R
R
2
2
1
1
⋅
⋅
C
C
=
=
=
=
R
R
R
R
G
G
/
/
R
R
ω
ω
⋅
⋅
⋅
⋅
⋅
⋅
O
O
10
10
7
7
7
7
10
10
10
10
R
R
ω
ω
PWM
PWM
R
R
S
S
p
p
⋅
⋅
,
,
10
10
1 ( )
1 ( )
2
2
n
n
,
,
ESR
ESR
ESR
ESR
)
)
−
−
1
1
1
1
3
3
−
−
1
1
1 (
1 (
6
6
6
6
1
1
3
3
C
C
C
C
⋅
⋅
+
+
a dominant low-frequency pole F
and double poles at half the switching frequency.
Including the voltage divider (R
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F
at F
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
Therefore, the procedure of the voltage loop design for
the SC4525D can be summarized as:
(1) Plot the converter gain, i.e. control to feedback transfer
function.
22
22
⋅
⋅
⋅
⋅
O
O
O
O
⋅
⋅
+
+
/ s
/ s
1
1
1
1
3
3
3
3
22
22
,
,
,
,
R s
R s
0 .
0 .
0 .
0 .
3 .
3 .
1 .
1 .
3 .
3 .
-60
-60
P1
-30
-30
ω
ω
60
60
30
30
1 .
1 .
0
0
ESR
ESR
. The integrator is used to boost the gain at low






⋅
⋅






n
n
0.2K
0.2K
ω
ω
ω
ω
10
10
Q
Q
=
=
=
=
⋅
⋅
Z
Z
Figure 8. Bode plots for voltage loop design
p
p
10
10
C
C
15
15
15
15
+
+
=
=
≈
≈
3
3
O
O
s
s
)
)
3
3
R
R
R
R
9 .
9 .
=
=
9 .
9 .
2
2
1
1
ESR
ESR
C
C
=
=
. 0
. 0
/
/
dB
dB
dB
dB
1
1
O
O
12
12
ω
ω
Fp
Fp
45
45
C
C
,
,
2
2
n
n
O
O
pF
pF
)
)
nF
nF
2K
2K
12
12
12
12
,
,
Fz1
Fz1
FREQUENCY (Hz)
FREQUENCY (Hz)
ω
ω
Z1
Z
Z
, and a high frequency pole
=
=
Fc
Fc
20K
20K
R
R
4
ESR
ESR
P
1
1
and R
at
C
C
www.semtech.com
Fp1
Fp1
Fz
Fz
O
O
,
,
6
Fsw/2
Fsw/2
), the control to
SC4525D
200K
200K
2M
2M
13