PCI2050GHK

Manufacturer Part NumberPCI2050GHK
DescriptionIC PCI-PCI BRIDGE 32-BIT 209-BGA
ManufacturerTexas Instruments
PCI2050GHK datasheet
 


Specifications of PCI2050GHK

ApplicationsPCI-to-PCI BridgeInterfacePCI
Voltage - Supply3 V ~ 3.6 VPackage / Case209-BGA MICROSTAR
Mounting TypeSurface MountPci Bus TypePCI To PCI Bridge
Supply Voltage Range3.3V To 5VOperating Temperature Range0°C To +70°C
Digital Ic Case StyleBGANo. Of Pins209
Filter TerminalsSMDRohs CompliantNo
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-9635-5
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PCI2050, PCI2050I
PCI to PCI Bridge
Data Manual
2003
PCI Bus Solutions
SCPS053B

PCI2050GHK Summary of contents

  • Page 1

    PCI2050, PCI2050I PCI to PCI Bridge 2003 Data Manual PCI Bus Solutions SCPS053B ...

  • Page 2

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment ...

  • Page 3

    Section 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    PCI Power Management 3.17.1 4 Bridge Configuration Header 4.1 Vendor ID Register 4.2 Device ID Register 4.3 Command Register 4.4 Status Register 4.5 Revision ID Register 4.6 Class Code Register 4.7 Cache Line Size Register 4.8 Primary ...

  • Page 5

    GPIO Input Data Register 5.8 Secondary Clock Control Register 5.9 P_SERR Status Register 5.10 Power-Management Capability ID Register 5.11 Power-Management Next-Item Pointer Register 5.12 Power-Management Capabilities Register 5.13 Power-Management Control/Status Register 5.14 PMCSR Bridge Support Register 5.15 Data Register ...

  • Page 6

    Figure 2–1 PCI2050 GHK Terminal Diagram 2–2 PCI2050 ZHK Terminal Diagram 2–3 PCI2050 PDV Terminal Diagram 3–1 System Block Diagram 3–2 PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–3 PCI AD31–AD0 During Address Phase of a ...

  • Page 7

    List of Tables Table 2–1 208-Terminal PDV Signal Names Sorted by Terminal Number 2–2 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number 2–3 Signal Names Sorted Alphabetically 2–4 Primary PCI System Terminals 2–5 Primary PCI Address and Data Terminals 2–6 ...

  • Page 8

    ... Introduction 1.1 Description The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high-performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently ...

  • Page 9

    ... MicroStar BGA and TI are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. 1.5 Ordering Information ORDERING NUMBER PCI2050PDV 3.3 V, 5-V tolerant I/Os PCI2050IPDV 3.3 V, 5-V tolerant I/Os PCI2050GHK 3.3 V, 5-V tolerant I/Os PCI2050IGHK 3.3 V, 5-V tolerant I/Os PCI2050ZHK 3.3 V, 5-V tolerant I/Os 1–2 VOLTAGE ...

  • Page 10

    Terminal Descriptions The PCI2050 device is packaged either in a 209-terminal GHK MicroStar BGA BGA , or a 208-terminal PDV package. Figure 2– GHK-package terminal diagram. Figure 2– ZHK-package terminal diagram. Figure 2– ...

  • Page 11

    V CC 157 GND 158 S_AD11 159 160 GND S_AD12 161 162 S_AD13 V CC 163 S_AD14 164 S_AD15 165 166 GND 167 S_C/BE1 168 S_PAR 169 S_SERR V CC 170 171 S_PERR 172 S_LOCK 173 S_STOP GND 174 S_DEVSEL ...

  • Page 12

    Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number PDV PDV SIGNAL NAME SIGNAL NAME NO. NO BPCCE 2 S_REQ1 45 P_CLK 3 S_REQ2 46 P_GNT 4 S_REQ3 47 P_REQ 5 S_REQ4 48 GND 6 ...

  • Page 13

    Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number (Continued) PDV PDV SIGNAL NAME NO. NO. 173 S_STOP 182 174 GND 183 175 S_DEVSEL 184 176 S_TRDY 185 177 S_IRDY 186 178 V CC 187 179 S_FRAME 188 180 ...

  • Page 14

    Table 2–2. 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number GHK/ZHK GHK/ZHK SIGNAL NAME NO. NO S_AD29 E9 A6 GND E10 A7 S_AD24 E11 E12 A9 S_AD18 E13 A10 S_C/BE2 E14 A11 ...

  • Page 15

    Table 2–2. 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number (Continued) GHK/ZHK GHK/ZHK SIGNAL NAME NO. NO. T1 GND U13 T19 V CC U14 U5 GND U15 U6 GND V5 U7 P_C/BE3 V6 U8 P_AD22 V7 U9 P_AD19 V8 U10 ...

  • Page 16

    Table 2–3. Signal Names Sorted Alphabetically SIGNAL PDV GHK/ZHK SIGNAL NAME NO. NO. NAME BPCCE GND 12 G3 P_AD0 GND 20 J2 P_AD1 GND 31 L3 P_AD2 GND 37 M6 P_AD3 GND 48 P6 P_AD4 GND 52 ...

  • Page 17

    Table 2–3. Signal Names Sorted Alphabetically (Continued) SIGNAL PDV GHK/ZHK SIGNAL NAME NO. NO. NAME S_V CCP 135 J17 V CC TCK 133 J19 V CC TDI 129 K18 V CC TDO 130 K17 V CC TMS 132 K14 V ...

  • Page 18

    The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see Table 2–4 through Table 2–12). The terminal numbers are listed for convenient reference. Table 2–4. Primary PCI System Terminals TERMINAL I/O PDV GHK/ZHK ...

  • Page 19

    Table 2–6. Primary PCI Interface Control Terminals TERMINAL I/O PDV GHK/ZHK NAME NO. NO. P_DEVSEL 84 P11 I/O 80 P10 I/O P_FRAME P_GNT P_IDSEL P_IRDY 82 V11 I/O P_LOCK 87 V12 I/O P_PAR 90 ...

  • Page 20

    Table 2–7. Secondary PCI System Terminals TERMINAL I/O PDV GHK/ZHK NAME NO. NO. S_CLKOUT9 S_CLKOUT8 39 N1 S_CLKOUT7 38 M5 S_CLKOUT6 Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each ...

  • Page 21

    Table 2–8. Secondary PCI Address and Data Terminals TERMINAL I/O PDV GHK/ZHK NAME NO. NO. 206 E6 S_AD31 204 F6 S_AD30 203 A5 S_AD29 S_AD28 201 E7 200 B6 S_AD27 S_AD26 198 F7 197 C7 S_AD25 S_AD24 195 A7 192 ...

  • Page 22

    Table 2–9. Secondary PCI Interface Control Terminals TERMINAL I/O PDV GHK/ZHK NAME NO. NO. Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the S_IRDY 177 C11 I/O current data phase of the transaction. A ...

  • Page 23

    TERMINAL PDV GHK/ZHK NAME NO. NO. BPCCE 44 P2 GPIO3/HSSWITCH 24 K1 GPIO2 25 K2 GPIO1 27 K5 GPIO0 28 K6 HSENUM 127 L14 HSLED 128 K19 155 E17 MS0 106 R17 MS1 102 R14 NC 125 L17 S_M66ENA 153 ...

  • Page 24

    Feature/Protocol Descriptions The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3–1 shows a simplified block diagram of a typical system implementation using the PCI2050. Host Bus CPU Host Bridge PCI Bus 0 ...

  • Page 25

    PCI Commands The bridge responds to PCI bus cycles as a PCI target device based on internal register settings and on the decoding of each address phase. Table 3–1 lists the valid PCI bus cycles and their encoding on ...

  • Page 26

    In this case, the bridge does not assert DEVSEL, and the configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles by accessing internal registers ...

  • Page 27

    Table 3–2. PCI S_AD31–S_AD16 During the Address NUMBER 3.4 Special Cycle Generation The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1 configuration cycle, if the bus number field ...

  • Page 28

    PCI2050 Figure 3–5. Secondary Clock Block Diagram 3.6 Bus Arbitration The PCI2050 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus arbitration. Nine secondary bus requests and nine secondary bus grants are provided on the secondary ...

  • Page 29

    Including the bridge, there are a total of ten potential secondary bus masters. These request and grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ8–S_REQ1 and S_GNT8–S_GNT1 are placed in a ...

  • Page 30

    Master Abort on Posted Writes If bit 4 in the P_SERR event disable register (PCI offset 64h, see Section 5. and a posted write transaction results in a master abort, then the PCI2050 signals SERR on the ...

  • Page 31

    The PCI Local Bus Specification recommends that a bridge wait 2 before discarding the transaction data or status. The PCI2050 implements a discard timer for use in delayed transactions. After a delayed transaction is ...

  • Page 32

    Table 3–3. Configuration via MS0 and MS1 MS1 MS0 3.14 CompactPCI Hot-Swap Support The PCI2050 is hot-swap friendly silicon that supports all of the hot-swap capable features, contains support for software control, and integrates ...

  • Page 33

    JTAG Support The PCI2050 implements a JTAG test port based on IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The JTAG test port consists of the following: A 5-wire test access port A test access port ...

  • Page 34

    Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN PDV TERMINAL REGISTER NO. NUMBER 20 167 21 168 22 169 23 171 24 172 25 173 26 – 27 175 28 176 29 177 30 179 31 180 32 182 ...

  • Page 35

    Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN PDV TERMINAL REGISTER NO. NUMBER ...

  • Page 36

    Table 3–5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN PDV TERMINAL REGISTER NO. NUMBER 105 70 106 71 107 73 108 74 109 76 110 77 111 – 112 79 113 80 114 82 115 83 116 84 117 85 ...

  • Page 37

    GPIO Interface The PCI2050 implements a four-terminal general-purpose I/O interface. Besides functioning as a general-purpose I/O interface, the GPIO terminals can be used to read in the secondary clock mask and to stop the bridge from accepting I/O and ...

  • Page 38

    PCI Power Management The PCI Power Management Specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of ...

  • Page 39

    Bridge Configuration Header The PCI2050 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Specification 1.1. Table 4–1 shows the PCI configuration header, which includes the predefined portion of the bridge configuration ...

  • Page 40

    Vendor ID Register This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this device. The vendor ID assigned 104Ch. Bit Name Type ...

  • Page 41

    Command Register The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table ...

  • Page 42

    Status Register The status register provides device information to the host system. Bits in this register are cleared by writing the respective bit; writing bit location has no effect. Table 4–3 describes ...

  • Page 43

    Revision ID Register The revision ID register indicates the silicon revision of the PCI2050. Bit 7 6 Name Type R R Default 0 0 Register: Revision ID Type: Read-only Offset: 08h Default: 00h (reflects the current revision of the ...

  • Page 44

    Primary Latency Timer Register The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from ...

  • Page 45

    Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read. Bit Name Type Default Bit 15 ...

  • Page 46

    Secondary Bus Number Register The secondary bus number register indicates the secondary bus number to which the bridge is connected. The PCI2050 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine ...

  • Page 47

    I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable ...

  • Page 48

    Secondary Status Register The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a ...

  • Page 49

    Memory Base Register The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of ...

  • Page 50

    Prefetchable Memory Limit Register The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this ...

  • Page 51

    Prefetchable Limit Upper 32 Bits Register The prefetchable limit upper 32 bits register plus the prefetchable memory limit register defines the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward ...

  • Page 52

    Capability Pointer Register The capability pointer register provides the pointer to the PCI configuration header where the PCI power management register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The ...

  • Page 53

    Interrupt Pin Register The bridge default state does not implement any interrupt terminals. Reads from bits 7–0 of this register return 0s. Bit 7 6 Name Type R R Default 0 0 Register: Interrupt pin Type: Read-only Offset: 3Dh ...

  • Page 54

    Table 4–5. Bridge Control Register Description (continued) BIT TYPE Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. If this bit is set, the ...

  • Page 55

    Extension Registers The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h–FFh in PCI configuration space in the PCI2050). These registers can be accessed through configuration reads and writes. ...

  • Page 56

    Extended Diagnostic Register The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset both the PCI2050 and the secondary bus. Bit 7 6 Name Type ...

  • Page 57

    Arbiter Control Register The arbiter control register is used for the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The PCI2050 bridge is the only secondary bus initiator that defaults to the higher priority arbitration ...

  • Page 58

    P_SERR Event Disable Register The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events are enabled by default. Bit 7 6 Name Type R R/W Default 0 0 Register: P_SERR event ...

  • Page 59

    GPIO Output Data Register The GPIO output data register controls the data driven on the GPIO terminals configured as outputs. If both an output-high bit and an output-low bit are set for the same GPIO terminal, the output-low bit ...

  • Page 60

    GPIO Input Data Register The GPIO input data register returns the current state of the GPIO terminals when read. Bit 7 6 Name Type R R Default X X Register: GPIO input data Type: Read-only Offset: 67h Default: X0h ...

  • Page 61

    Secondary Clock Control Register The secondary clock control register is used to control the secondary clock outputs. Bit Name Type R R/W R/W R/W Default Register: Secondary clock control Type: Read-only, ...

  • Page 62

    P_SERR Status Register The P_SERR status register indicates what caused a SERR event on the primary interface. Bit 7 6 Name Type R R/W Default 0 0 Register: P_SERR status Type: Read-only Read/Write Offset: 6Ah Default: 00h Table 5–9. ...

  • Page 63

    Power-Management Next-Item Pointer Register The power-management next-item pointer register is used to indicate the next item in the linked list of PCI power-management capabilities. The next-item pointer returns E4h in CompactPCI mode, indicating that the PCI2050 supports more than ...

  • Page 64

    Power-Management Control/Status Register The power-management control/status register determines and changes the current power state of the PCI2050. The contents of this register are not affected by the internally generated reset caused by the transition from D3 state. Bit 15 ...

  • Page 65

    PMCSR Bridge Support Register The PMCSR bridge support register is required for all PCI bridges and supports PCI-bridge-specific functionality. Bit 7 6 Name Type R R Default X X Register: PMCSR bridge support Type: Read-only Offset: E2h Default: X0h ...

  • Page 66

    HS Capability ID Register The HS capability ID register identifies the linked list item as the register for cPCI hot-swap capabilities. The register returns 06h when read, which is the unique ID assigned by the PICMG for PCI location ...

  • Page 67

    Hot-Swap Control Status Register The hot-swap control status register contains control and status information for cPCI hot swap resources. Bit 7 6 Name Type R R Default 0 0 Register: Hot-swap control status Type: Read-only, Read/Write Offset: E6h Default: ...

  • Page 68

    Electrical Characteristics 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range ...

  • Page 69

    Recommended Operating Conditions for PCI Interface V CC Core voltage P V P_V CCP PCI supply voltage PCI supply voltage S V S_V CCP PCI supply voltage PCI supply voltage Input voltage Input voltage V † ...

  • Page 70

    PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (see Note 5 and Figure 6–1 and Figure 6–4) PCLK to shared signal valid delay time Propagation delay time Propagation delay time PCLK ...

  • Page 71

    Parameter Measurement Information LOAD CIRCUIT PARAMETERS C LOAD † TIMING I OL PARAMETER (pF) (mA) t PZH PZL t PHZ t dis PLZ † C LOAD includes ...

  • Page 72

    PCI Bus Parameter Measurement Information 0 PCLK RSTIN PCLK 1.5 V PCI Output PCI Input Figure 6–4. Shared-Signals Timing Waveforms Figure 6–2. PCLK Timing Waveform t ...

  • Page 73

    ... Mechanical Data GHK (S-PBGA-N209) 16,10 SQ 15,90 0,95 0,85 0,55 0,12 0,08 0,45 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments. 0, 1,40 MAX Seating Plane 0,10 M 0,45 0,35 ...

  • Page 74

    ... ZHK (S-PBGA-N257) 16,10 15,90 0,95 0,85 0,55 0,45 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration. D. This package is lead-free. MicroStar is a trademark of Texas Instruments. 7– Corner 1,40 MAX Seating Plane 0,08 0,12 0,45 0,35 ...

  • Page 75

    PDV (S-PQFP-G208) 156 157 208 1 25,50 TYP 28,05 27,95 30,20 29,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 105 104 ...