PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet
PEB2255H-V13
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PEB2255H-V13IN
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PEB2255H-V13 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... Revision History: Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com 2000-07 Preliminary Data Sheet DS1 DS 1 ...
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Preface ® The FALC -LH framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The digital functions as well as the analog characteristics are configured ...
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Organization of this Document This Data Sheet is organized as follows: • Chapter 1, Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. • Chapter 2, Pin Descriptions Lists ...
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Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ANSI/EIA-656 ANSI T1.102 ANSI T1.403 AT&T PUB 43802 AT&T PUB 54016 AT&T PUB 62411 ESD Ass. Standard EOS/ESD-5.1-1993 ETSI ETS 300 011 ETIS ETS 300 166 ETSI ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.3.1.4 Channel Associated Signaling CAS (E1, µP access mode 4.3.2 Transmit Elastic Buffer (E1 ...
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Table of Contents 5.1.4 Receive Line Coding (T1/J1 ...
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Table of Contents 5.5.2 Auto Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 8.3.10 Bit Oriented Message Mode (T1/J1 176 8.3.10.1 Data Link Access ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 Transmit System Interface Clocking: 8 MHz/4 Mbit/s (T1/J1 125 Figure 44 2.048 Mbit/s Transmit Signaling Clocking (T1/J1 ...
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List of Tables Table 1 Pin Definitions - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . 25 Table 2 Pin Definitions - Line Interface ...
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List of Tables Table 43 HDLC Controller Initialization (E1 162 Table 44 CAS-CC ...
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Introduction ® The FALC -LH framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway, H.100 or H-MVIP bus for world market telecommunication systems. Due to ...
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E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications ® FALC -LH Version 1.3 1.1 Features Line Interface • High density, generic interface for all E1/T1/J1 applications • Analog receive and transmit circuitry for long haul and ...
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Frame Aligner • Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 (E1) and for 1544 kbit/s according to ITU-T G.704 and JT G.704 (T1/J1) • Programmable frame formats : E1: Doubleframe, CRC Multiframe (E1) T1: 4-Frame Multiframe (F4,FT), 12-Frame ...
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Provides access to serial signaling data streams • CAS Multiframe synchronization and synthesis according to ITU-T G.732 • Alarm insertion and detection (AIS and LOS in Timeslot 16) • Transparent mode • FIFO buffers (64 bytes deep) for efficient ...
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Logic Symbol ROID RL1 / RDIP / ROID Receive RL2 / RDIN / RCLKI Line REFR Interface V V TDI Boundary TMS Scan TCK TDO XL1M XL1 / XDOP / XOID Transmit Line XL2 / XDON Interface XL2M XOID ...
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Typical Applications The figures show a multiple link circuit for Frame Relay applications using the FALC-LH together with the 128 channel HDLC controller M128X and the Memory Timeswitch MTLS as well channel interface to the ATM ...
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Port 1 FALC PEB 2255 Port 8 FALC PEB 2255 Figure 3 8 Channel E1/T1/J1 Interface to the ATM Layer • ® FALC -LH PEB 2255 ® FALC -LH ...
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Pin Descriptions 2.1 Pin Diagram (top view) • 60 XMFS 61 SCLKX 62 SCLKR 63 SYPX 64 SYPR /RFM 65 FSC 66 67 RMFB XMFB /XOID 68 DLX 69 DLR/RSIG 70 FREEZS/RFSP 71 RCLK ...
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Pin Definitions and Functions • • Table 1 Pin Definitions - Microprocessor Interface Pin No. Symbol 42...48 A0 … 41…38 D0…D3 35…28 D4…D11 25…22 D12..D15 49 ALE 52 CS Data Sheet Input (I) Function Output (O) Supply ...
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Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin No. Symbol 50 RD/DS 51 WR/RW 11 DBW 8 IM Data Sheet Input (I) Function Output (O) Supply (S) I Read Enable (Intel bus mode) This signal indicates a read operation. ...
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Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin No. Symbol 53 BHE/BLE INT Data Sheet Input (I) Function Output (O) Supply (S) Bus High Enable (Intel bus mode) If 16-bit bus interface mode is enabled, ...
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Table 2 Pin Definitions - Line Interface Pin No. Symbol 2 RL1 RDIP ROID 80 ROID Data Sheet Input (I) Function Output (O) Supply (S) Line Interface Receive I (analog) Line Receiver 1 Analog Input from the external transformer. ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin No. Symbol 4 RL2 RDIN RCLKI Data Sheet Input (I) Function Output (O) Supply (S) I (analog) Line Receiver 2 Analog Input from the external transformer. Selected if LIM1.DRS = 0. ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin No. Symbol 15 XL1 XDOP XOID Data Sheet Input (I) Function Output (O) Supply (S) Line Interface Transmit O (analog) Transmit Line 1 Analog output to the external transformer. Selected if ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin No. Symbol 17 XL1M 13 XL2 XDON 12 XL2M Data Sheet Input (I) Function Output (O) Supply (S) I Transmit Line 1 Monitor Analog input from external transmit transformer (XL1). This ...
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Table 3 Pin Definitions - Clock Generation Pin No. Symbol 7 XTAL1 6 XTAL2 10 XTAL3 9 XTAL4 79 XCLK FSC Data Sheet Input (I) Function Output (O) Supply (S) I Crystal Connection 16.384 MHz A pullable crystal of ...
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Table 3 Pin Definitions - Clock Generation (cont’d) Pin No. Symbol 66 FSC 75 CLK16M 76 CLK12M 77 CLK8M 78 CLKX 60 SYNC Data Sheet Input (I) Function Output (O) Supply ( kHz Frame Synchronization Pulse is output ...
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Table 3 Pin Definitions - Clock Generation (cont’d) Pin No. Symbol 80 SYNC2 72 RCLK Data Sheet Input (I) Function Output (O) Supply (S) I Clock Synchronization 2 Secondary reference clock for internal transmit clock generation. The clock frequency is ...
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Table 4 Pin Definitions - System Interface Pin No. Symbol 57 RDO 70 DLR RSIG Data Sheet Input (I) Function Output (O) Supply (S) System Interface Receive O Receive Data Out Received data which is sent to the system ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 71 RFSP FREEZS Data Sheet Input (I) Function Output (O) Supply (S) O Receive Frame Synchronous Pulse E1: FMR3.CFRZ = 0 T1/J1: XC0.SFRZ = 0 Active low framing pulse ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 65 SYPR RFM 63 SCLKR Data Sheet Input (I) Function Output (O) Supply (S) I Synchronous Pulse Receive SIC2.SRFSO = 0 (reset value): Defines the beginning of time slot ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 58 RSIGM 67 RMFB Data Sheet Input (I) Function Output (O) Supply (S) O Receive Signaling Marker E1/T1/J1 mode: Marks the time-slots which are defined by register RTR1-4 of ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 68 XMFB XOID Data Sheet Input (I) Function Output (O) Supply (S) System Interface Transmit O Transmit Multiframe Begin E1 mode/LOOP.SPN = 0: Marks the begin of every transmitted ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 64 SYPX 62 SCLKX 55 XDI Data Sheet Input (I) Function Output (O) Supply (S) I Synchronous Pulse Transmit Defines the beginning of time slot 0 at system highway ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 69 DLX 80 XSIG Data Sheet Input (I) Function Output (O) Supply (S) O Data Link Bit Transmit E1 mode: Marks the S stream on XDI. The S slot ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin No. Symbol 59 XSIGM 61 XMFS Data Sheet Input (I) Function Output (O) Supply (S) O Transmit Signaling Marker Marks the transmit time slots which are defined by register TTR1-4 of ...
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Table 5 Pin Definitions - Miscellaneous Pin No. Symbol V 1 DDR V 5 SSR V 16 DDX V 14 SSX V 27, 37 26, 36 RES Data Sheet Input (I) Function Output ...
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Table 5 Pin Definitions - Miscellaneous (cont’d) Pin No. Symbol 3 REFR Boundary Scan/Joint Test Access Group (JTAG) 18 TDI 19 TMS 20 TCK 21 TDO 1) XTAL3 not required in E1/bypass mode 2) Boundary scan reset is done automatically ...
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Functional Description E1/T1/J1 3.1 Functional Overview ® The FALC -LH device contains analog and digital function blocks, which are configured and controlled by an external microprocessor or microcontroller. The main interfaces are • Receive and Transmit Line Interface • ...
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Block Diagram • SYPR RDO RMFB ROID RL1 / RL2 RDIP / RDIN ROID / RCLKI Figure 6 Block Diagram Data Sheet RSIGM XSIGM XDI SYPX DLR / RSIG DLX XMFB XSIG XMFS Local Loop XL1 / XL2 XDOP ...
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Functional Blocks 3.3.1 Microprocessor Interface The communication between the CPU and the FALC accessible registers. The interface may be configured as Intel or Motorola type with a selectable data bus width bits. The CPU transfers ...
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Table 6 Data Bus Access (16-Bit Intel Mode) BHE A0 Register Access 0 0 FIFO word access Register word access (even addresses Register byte access (odd addresses Register byte access (even addresses transfer ...
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FIFO Structure In transmit and receive direction of the signaling controller 64-byte deep FIFOs are provided for the intermediate storage of data between the system internal highway and the CPU interface. The FIFOs are divided into two halves of ...
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RFIFO Byte 4 3 Byte 3 2 Byte 2 1 Byte 1 D15 D8 D7 Figure 8 FIFO Word Access (Motorola Mode) 3.3.1.3 Interrupt Interface Special events in the FALC programmable characteristics (open drain, push-pull; IPC ...
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ISR5 IMR5 Figure 9 Interrupt Status Registers Each interrupt indication of registers ISR0…3,5 can be selectively masked by setting the corresponding bit in the corresponding mask registers IMR0…3,5. If the interrupt status bits are masked they neither generate an interrupt ...
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Note: In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired, care must ...
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Test Access Port TCK CLOCK TMS Test Control TDI Data IN TDO Enable Data OUT Figure 10 Block Diagram of Test Access Port and Boundary Scan Test handling is performed via the pins TCK (Test Clock), TMS (Test Mode Select), ...
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Functional Description E1 4.1 Receive Path in E1 Mode RL1/RDIP/ROID Equalizer RL2/RDIN/RCLKI Figure 11 Receive Clock System (E1) Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 ...
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Long Haul Interface ® The FALC -LH has an integrated short-haul and long-haul line interface, consisting of a receive equalization network and noise filtering. 4.1.1 Receive Equalization Network (E1) ® The FALC -LH automatically recovers the signals received on pins ...
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The 1T2B decoder does not correct any errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI. The HDB3 code is ...
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Loss of Signal Detection (E1) There are different definitions for detecting Loss of Signal (LOS) alarms in the ITU-T G.775 and ETS 300233. The FALC is performed by generating an interrupt (if not masked) and activating a status bit. ...
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Receive Jitter Attenuator (E1) The receive jitter attenuator is placed in the receive path. The jitter attenuator meets the requirements of ITU-T I.431, G. 736-739, G.823 and ETSI TBR12/13. The internal DCO-R generates a “jitter free“ output clock which ...
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Table 10 System Clocking (E1) Mode Internal LOS Active Master independent Fixed to Master independent 2 MHz Slave no Slave no Slave yes Slave yes The jitter attenuator meets the jitter transfer requirements of the recommendations I.431 and G.735-739 ...
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Jitter Tolerance (E1) ® The FALC -LH receiver’s tolerance to input jitter complies to ITU for CEPT application. Figure 14 shows the curves of different input jitter specifications stated below as well as ® the FALC -LH performance. 1000 ...
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Transmit Jitter Attenuator (E1) The transmit jitter attenuator DCO-X circuitry generates a “jitter free“ transmit clock and meets the following requirements: ITU-T I.431, G. 703, G. 736-739, G.823 and ETSI TBR12/13. The DCO-X circuitry works internally with the same ...
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XCLK Figure 15 Transmit Clock System (E1) Note Dual Rail Interface DCO-R Digital Controlled Oscillator Receive DCO-X Digital Controlled Oscillator Transmit 4.1.10 Framer/Synchronizer The following functions are performed: • Synchronization on pulse frame and multiframe • Error indication ...
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Generation of control signals to synchronize the CRC checker and the receive elastic buffer. If programmed and applicable to the selected multiframe format, CRC checking of the incoming data stream is done by generating check bits for a CRC ...
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RDO. If the receive buffer is bypassed, data is clocked off with RCLK instead of SCLKR. In one frame or short buffer mode the delay through the receive buffer is reduced to an average delay ...
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In single frame mode ( SIC1. RBS), values of receive time slot offset (RC1/0) have to be specified great enough to prevent too great approach of frame begin (line side) and frame begin (system side). Figure 16 gives an idea ...
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Receive Signaling Controller (E1) The signaling controller can be programmed to operate in various signaling modes. The ® FALC -LH performs the following signaling and data link methods: 4.1.12.1 HDLC or LAPD access In case of common channel signaling ...
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The complete CAS multiframe can be transmitted on pin RSIG. The signaling data is clocked with the working clock of the receive highway in conjunction with the receive synchronization pulse (SYPR/RFM). Data on RSIG is transmitted in the last 4 ...
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SYPR SCLKR T TS31 TS0 RDO FAS / NFAS RSIG T = Time-Slot Offset (Register RC1/0) FAS = Frame ...
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System Interface in E1 Mode ® The FALC -LH offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. The interface to the receive system highway is realized ...
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SYNC Receive Clock Receive Data Transmit Data BY P Transmit Clock Figure 18 System Interface (E1) Data Sheet Receive Jitter Attenuator Receive Elastic Receive Buffer Backplane PLB Transmit Elastic Transmit Buffer Backplane Transmit Jitter Attenuator 70 ...
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FRAME 1 FRAME 2 FRAME 3 RDO RMFB SYPR SYPR Trigger 1) Edge SCLKR 8.192 MHz SCLKR 2.048 MHz RDO/RSIG Bit 255 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data Rate (SCLKR = 8.192 MHz) RDO/RSIG 4 Mbit/s Data ...
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Time Slot Assigner (E1) ® The FALC -LH offers the flexibility to connect data during certain time slots, as defined by registers RTR1-4 and TTR1-4, to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed ...
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Transmit Path in E1 Mode Compared to the receive path the inverse functions are performed for the transmit direction. The interface to the transmit system highway is realized by two data buses, one for the data XDI and one ...
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XDI FRAME0 FRAME1 XMFB XMFS SYPX Trigger Edge SYPX T SCLKX XSIGM XDI/XSIG DLX Sa-Bit Marker XC0.SA8E-SA4E 1) delay T is programmable by XC0/1; Figure 20 Transmit System Interface Clocking: 2.048 MHz (E1) Data Sheet Multi Frame 1 FRAME2 FRAME15 ...
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XDI FRAME0 FRAME1 XMFB XMFS SYPX Trigger Edge SYPX SCLKX XSIGM Time-Slot Marker TTR1...4 RC0.SICS = 0 XDI/XSIG RC0.SICS = 0 XDI/XSIG RC0.SICS = 1 DLX Sa-Bit Marker XC0.SA8E-SA4E RC0.SICS = 0 DLX Sa-Bit Marker XC0.SA8E-SA4E RC0.SICS = 0 1) ...
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Transmit Signaling Controller (E1) Similar to the receive signaling controller the same signaling methods and the same time slot assignment is provided. The FALC link methods: 4.3.1.1 HDLC or LAPD access The transmit signaling controller of the FALC generation, ...
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If the FALC -LH is optioned for no signaling, the data stream from the system interface ® passes the FALC -LH undisturbedly. • SYPX SCLKX T TS31 TS0 ...
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XBS1 short buffer or 92 bits : Max. wander amplitude: 18 µs average delay after performing a slip: 46 bits The functions of the transmit buffer are: • Clock adaption between system clock (SCLKX) and internally ...
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Auxiliary pattern generation The frame/multiframe boundaries of the transmitter may be externally synchronized by using the SYPX/XMFS pin. Any change of the transmit time slot assignment subsequently produces a change of the framing bit positions on the line side. ...
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Similar to the receive line interface three different data types are supported: • Ternary Signal Single rail data is converted into a ternary signal which is output on pins XL1 and XL2. The HDB3 and AMI line code is employed. ...
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Figure 24 Transmit Line Monitor Configuration (E1) Data Sheet XPM2.DAXLT/XLT XL2M Line XL1M Monitor TRI XL1 XL2 81 PEB 2255 FALC-LH V1.3 Functional Description E1 R FALC -LH Pulse Shaper XDATA ITS09746 2000-07 ...
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Framer Operating Modes (E1) 4.4.1 General Bit: FMR1.PMOD = 0 PCM line bit rate : Single frame length : Framing frequency : HDLC controller : Organization : The operating mode of the FALC and characteristics, line code, multiframe structure, ...
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Doubleframe Format (E1) The framing structure is defined by the contents of time slot 0 (refer to Table 17 Allocation of Bits Time Slot 0 (E1) Bit Number Alternate Frames Frame Containing the Frame Alignment ...
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Table 18 Transmit Transparent Mode (Doubleframe E1) Enabled by Framing – (int. generated) XSP.TT0 via pin XDI TSWM.TSIF (int. generated) TSWM.TSIS (int. generated) TSWM.TRA (int. generated) TSWM.TSA4-8 (int. generated) 1) pin XDI or XSIG or XFIFO-Buffer (signaling controller) 2) ...
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The resynchronization procedure starts automatically after reaching the asynchronous state. Additionally, it may be invoked user controlled via bit: FMR0.FRS (Force Resynchronization: the FAS word detection is interrupted until the framer is in the asynchronous state. After that, resynchronization starts ...
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CRC-Multiframe (E1) The multiframe structure shown in FMR2.RFS1/0 for the receiver and FMR1.XFS for the transmitter. Multiframe : Frame alignment : Multiframe alignment : CRC bits : CRC block size : CRC procedure : Table 19 CRC-Multiframe Structure (E1) ...
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For transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode (see also Table 20 Transmit Transparent Mode (CRC Multiframe E1) enabled by Framing + CRC – (int. generated) XSP.TT0 via pin XDI TSWM.TSIF via ...
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In doubleframe asynchronous state, counting of framing errors, CRC4 bit errors and detection of remote alarm is stopped. AIS is automatically sent to the backplane interface (can be disabled via bit FMR2.DAIS). Further on the updating of the registers RSA6S ...
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The research of the basic frame alignment is done in parallel and is independent of the synchronization procedure of the primary basic ...
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S - Bit Access (E1) a Due to signaling procedures using the five S CRC multiframe structure, three possibilities of access via the microprocessor are implemented. • The standard procedure allows reading/writing the S further support. The S a ...
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Sa6 Bit Error Indication Counters The Sa6 bit error indication counter CRC2L/H (16 bits) counts the received Sa6 bit sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital section this counter option gives information about ...
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Incrementing is only possible in the multiframe synchronous state. Note: E-bits may be processed via the system interface. Setting bit TSWM.TSIS enables transparency for E bits in transmit direction (refer to OUT of Primary BFA: IN ...
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Additional Functions (E1) 4.5.1 Error Performance Monitoring and Alarm Handling Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled via bit FMR1.XAIS. Loss of Signal: Detection and recovery is flagged by bit ...
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Table 21 Summary of Alarm Detection and Release (E1) (cont’d) Alarm Detection Condition Remote Alarm in Y-bit = 1 received in CAS time slot 16 (TS16RA) multiframe alignment word Loss of Signal in all zeros for at least 16 time ...
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Automatic clock source switching In Slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock. In case of Loss of Signal LOS the DCO-R switches automatically to Master mode. • Automatic freeze signaling: Updating of the ...
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The user defined loop up and loop down pattern is programmable individually from bit in length (LCR1.LAC1/0 and LCR1.LDC1/0). Programming of loop codes is done in registers LCR2 and LCR3. Status and interrupt status bits inform the ...
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Test Functions (E1) 4.6.1 Pseudo-Random Bit Sequence Generation and Monitor ® The FALC -LH has the ability to generate and monitor 2 bit sequences (PRBS). The generated PRBS pattern is transmitted optionally inverted or not to the remote end ...
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Payload Loop Back To perform an effective circuit test a payload loop is implemented. The payload loop back (FMR2.PLB) loops the data stream from the receiver section back to transmitter section. The looped data passes the complete receiver including ...
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Local Loop The local loopback mode, selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface are routed through the ...
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Single Channel Loop Back Each of the 32 time slots may be selected for loopback from the system PCM input (XDI) to the system PCM output (RDO). This loopback is programmed for one time slot at a time selected ...
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Alarm Simulation (E1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible ‘real’ alarm conditions are not reported to the processor when the device is in the ...
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Functional Description T1/J1 5.1 Receive Path in T1/J1 Mode RL1 / RDIP / ROID Equalizer RL2 / RDIN / RCLKI Figure 31 Receive Clock System (T1/J1) Receive Line Interface (T1/J1) For data input, three different data types are supported: ...
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Receive Short and Long Haul Interface (T1/J1) ® The FALC -LH has now an integrated short-haul and long-haul line interface, consisting of a receive equalization network, noise filtering and programmable line build-outs (LBO). 5.1.1 Receive Equalization Network (T1/J1) ® The ...
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NRZ coding, the decoder is by-passed and no code violations are detected. Additionally, the receive line interface contains the alarm detection for Alarm Indication Signal AIS (Blue Alarm) and the Loss of Signal LOS (Red Alarm). Pulse ...
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LOS criteria is defined by the equalizer status. The number N may be set via a 8 bit register PCD. The contents of the PCD register is multiplied by 16, which results in ...
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For some applications it might be useful starting of jitter attenuation at lower frequencies. Therefore the corner frequency is switchable by the factor of ten down to 0.6 Hz (LIM2.SCF). Jitter attenuation can be achieved either using an external tunable ...
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Table 23 System Clocking (T1/J1) (cont’d) Mode Internal LOS Active Slave yes Slave yes Slave yes The jitter attenuator meets the jitter transfer requirements of the PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499, I.431 and G. 703.(refer to ...
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Jitter Tolerance (T1/J1) ® The FALC -LH receiver’s tolerance to input jitter complies to ITU and Bellcore requirements for T1 applications. Figure 34 shows the curves of different input jitter specifications stated below as well as ® the FALC ...
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Output Jitter (T1/J1) According to the input jitter defined by PUB62411 the FALC jitter, which is specified in Table 24 Output Jitter (T1/J1) Specification Lower Cutoff PUB 62411 kHz 10 Hz 5.1.9 Transmit Jitter Attenuator (T1/J1) ...
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D A Pulse Shaper XCLK Figure 35 Transmit Clock System (T1/J1) Note Dual Rail Interface; DCO-X = Digital Controlled Oscillator Transmit 5.1.10 Framer/Synchronizer (T1/J1) The following functions are performed: • Synchronization on pulse frame and multiframe • Error ...
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Generation of control signals to synchronize the CRC checker and the receive elastic buffer. If programmed and applicable to the selected multiframe format, CRC checking of the incoming data stream is done by generating check bits for a CRC ...
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Frame alignment between system frame and receive route frame • Reporting and controlling of slips Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, time slot serial data which is circularly written ...
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Figure 36 gives an idea of operation of the receive elastic buffer: A slip condition is detected when the write pointer (W) and the read pointer (R) of the memory are nearly coincident, i.e. the read pointer is within the ...
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Table 26 Channel Translation Modes (T1/J1) (cont’d) Speech Channels C. Translation Mode – – – – – – ...
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Receive Signaling Controller (T1/J1) The signaling controller may be programmed to operate in various signaling modes. The ® FALC -LH performs the following signaling and data link methods. 5.1.12.1 HDLC/SDLC or LAPD Access In case of common-channel signaling the ...
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CAS Bit-robbing (T1/J1, µP access mode) The signaling information is carried in the LSB of every sixth frame for each time slot. The signaling controller samples the bit stream on the receive line side. ...
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Table 27 System Clock and Data Rates (T1/J1) System Data Rate 1.544 Mbit/s 2.048 Mbit/s 4.096 Mbit valid invalid Generally the data or marker on the system interface are clocked off or latched on the ...
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SYNC Receive Clock Receive Data Transmit Data BY P Transmit Clock Figure 37 System Interface (T1/J1) Data Sheet Receive Jitter Attenuator Receive Elastic Receive Buffer Backplane PLB Transmit Elastic Transmit Buffer Backplane Transmit Jitter Attenuator 118 ...
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RDO FRAME 1 FRAME 2 FRAME 3 RMFB SYPR SYPR Trigger 1) Edge SCLKR 8.192 MHz T SCLKR 1.544 MHz RDO/RSIG Bit 255 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data Rate Bit 0 (SCLKR = 8.192 MHz) Bit 255 ...
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SYPR SCLKR T TS31 TS0 RDO FS/DL-Channel RSIG Time-Slot Offset F = FS/DL-Bit ABCD = Signaling Bits for Time-Slot 1-24 Time-Slot Mapping acc. Channel Translation Mode 0 Figure ...
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Time Slot Assigner (T1/J1) ® The FALC -LH offers the flexibility to connect data during certain time slots, as defined by registers RTR1-4 and TTR1-4, to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed ...
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MSB 1 Figure 41 Receive FS/DL Bits in Time Slot 0 on RDO (T1/J1) Data Sheet FS/DL Time-Slot 122 PEB 2255 FALC-LH V1.3 Functional Description T1/J1 LSB 7 8 FS/DL FS/DL Data Bit ITD06460 2000-07 ...
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Transmit Path in T1/J1 Mode Compared to the receive paths the inverse functions are performed for the transmit direction. The interface to the transmit system highway is realized by two data buses, one for the data XDI and one ...
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XDI FRAME1 FRAME2 XMFB XMFS SYPX Trigger Edge SYPX T SCLKX XSIGM Time Slot Marker XDI DLX DL Bit Marker 1) delay T is programmable by XC0/1; Figure 42 Transmit System Interface Clocking: 1.544 MHz (T1/J1) Data Sheet FRAME3 FRAME12 ...
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XDI FRAME1 FRAME2 XMFS SYPX Trigger Edge SYPX SCLKX XSIGM Time-Slot Marker XTR1...4 RC0.SICS = 0 (1) XDI/XSIG RC0.SICS = 0 XDI/XSIG RC0.SICS = 1 DLX DL-Bit Marker RC0.SICS = 0 DLX DL-Bit Marker RC0.SICS = 1 1) delay T ...
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SYPX SCLKX T TS31 TS0 XDI FS/DL-Channel XSIG Time-Slot Offset F = FS/DL-Bit ABCD = Signaling Bits for Time-Slot 1-24 Time-Slot Mapping acc. Channel Translation Mode 0 Figure ...
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Frame 1 RD0 XDI RMFB XMFB FS/ RD0 XDI 1) RSIGM XSIGM FS/ RD0 XDI 1) RSIGM XSIGM 1) RSIGM and XSIGM are programed via registers RTR1 channel 24 Figure 46 Signaling Marker for ...
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Frame 1 RD0 XDI RMFB XMFB FS/ RD0 XDI 1) RSIGM XSIGM FS/ RD0 XDI 1) RSIGM XSIGM 1) RSIGM and XSIGM will mark the robbed bit positions if XCO.BRM is set high Figure ...
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Transmit Direction FS/DL data on system transmit highway (XDI), time slot 0. MSB 1 Figure 48 Transmit FS/DL Bits on XDI (T1/J1) 5.3.1 Transmit Signaling Controller (T1/J1) Similar to the receive signaling controller the same signaling methods and the same ...
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The FS/DL bit is sampled on port XSIG and inserted in the outgoing data stream. The received CAS multiframe is inserted frame aligned into the data stream on XDI. Data sourced by the internal signaling controller overwrites the external ...
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Transmit Elastic Buffer (T1/J1) The transmit elastic store with a size of max. 2 temporary store for the PCM data to adapt the system clock (SCLKX) to the internally generated clock for the transmit data, and to re-translate time ...
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Reporting and controlling of slips Writing of received data from XDI is controlled by SCLKX and SYPX/XMFS in conjunction with the programmed offset values for the transmit time slot/clock slot counters. Reading of stored data is controlled by the ...
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Transmitter (T1/J1) The serial bit stream is then processed by the transmitter which has the following functions: • Frame/multiframe synthesis of one of the four selectable framing formats • Insertion of service and data link information • AIS generation ...
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Transmit Line Interface (T1/J1) The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided by pin XDI and the digital transmitter. Similar to ...
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Programmable Pulse Shaper and Line Build-Out (T1/J1) In long haul applications the transmit pulse masks are optionally generated according to FCC68 and ANSI T1. 403. To reduce the crosstalk on the received signals the ® FALC -LH offers the ...
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Transmit Line Monitor (T1/J1) The transmit line monitor compares the transmit line pulses on XL1 and XL2 with the transmit input signals received on pins XL1M and XL2M. The monitor detects faults on the primary side of the transformer ...
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Framer Operating Modes (T1/J1) 5.4.1 General Activated with bit FMR1.PMOD = 1. PCM line bit rate : Single frame length : Framing frequency : Organization : Selection of one of the four permissible framing formats is performed by bits ...
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FRS0.LMFA SSP = 1:FT FS FRS0.LMFA ESF:ESF framing bits The resynchronization procedure may be controlled by either one of the following procedure: • Automatically (FMR4.AUTO = 1). Additionally, it may be triggered by the user by setting/resetting one of ...
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Auto-Mode Definite Candidate Multiple Candidates Depends on the Disturbance D One Disturbance : Figure 51 Influences on Synchronization Status (T1/J1) Data Sheet EXLS FRS DON DOFF Multiple Candidates EXLS, FRS FRS DON DOFF EXLS FRS 139 PEB ...
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Figure 51 gives an overview of influences on synchronization status for the case of different external actions. Activation of auto-mode and non-auto mode is performed via bit FMR4.AUTO. Generally, for initiating resynchronization it is recommended to use bit: FMR0.EXLS first. ...
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Table 34 12-Frame Multiframe Structure (T1/J1) Frame Number – – – – – – 1) This bit can be ...
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Extended Superframe (F24 or ESF Format, T1/J1) The use of the first bit of each frame for the multiframe alignment word, the data link bits, and the CRC bits is shown in • Table 35 Extended Superframe Structure (F24, ...
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ESF multiframe • 4 incorrect (1 out of 6) consecutive multiframes independent of CRC6 errors. There are four multiframe synchronization modes selectable via FMR2.MCSP and FMR2.SSP. • FMR2.MCSP/SSP = 00 In ...
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Remote Alarm (yellow alarm) Generation/Detection Remote alarm (yellow alarm) is indicated by the periodical pattern ‘1111 1111 0000 0000 …’ in the DL bits. Remote alarm is declared even in the presence of BER 1/1000. The alarm is reset ...
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Synchronization Procedure In the synchronous state terminal framing (FT bits) and multiframing (FS bits of the framing header) are observed independently. Further reaction on framing errors depends on the selected synchronization/resynchronization procedure (via bit FMR2.SSP): • FMR2.SSP = ‘0’: ...
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Table 36 72-Frame Multiframe Structure (T1/J1) Frame Number – – – – – – – 15 ...
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Summary of Frame Conditions (T1/J1) Table 37 Summary Frame Recover/Out of Frame Conditions (T1/J1) Format Frame Recover Condition F4 only one FT pattern found, optional forcing on next available FT framing candidate F12 (D4) FMR2.SSP = 0: Combined FT ...
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Additional Functions (T1/J1) 5.5.1 Error Performance Monitoring and Alarm Handling Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled via bit FMR1.XAIS. Loss of Signal: Detection and recovery is flagged by bit ...
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Table 38 Summary of Alarm Detection and Release (T1/J1) (cont’d) Alarm Detection Condition Yellow Alarm RC1.RRAM = 0: bit 255 consecutive time or slots or FS bit = 1 of frame12 in F12 (D4) Remote Alarm ...
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Auto Modes • Automatic remote alarm (Yellow Alarm) access If the receiver has lost its synchronization (FRS0.LFA) a remote alarm (yellow alarm) can be sent to the distant end automatically, if enabled by bit FMR2.AXRA. In synchronous state the ...
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Clear Channel Capability For support of common T1 applications, clear channels can be specified via the 3-byte register bank CCB1 … CCB3. In this mode the contents of selected transmit time slots are not overwritten by internally or externally ...
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Pulse Density Detection ® The FALC -LH examines the receive data stream on the pulse density requirement which is defined by ANSI T1. 403. More than 15 consecutive zeros or less than 23 ones in each and every time ...
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Remote Loop In the remote loopback mode the clock and data recovered from the line inputs RL1/2 or RDIP/RDIN are routed back to the line outputs XL1/2 or XDOP/XDON via the analog or digital transmitter normal mode ...
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Payload Loop Back To perform an effective circuit test a line loop is implemented. If the payload loopback (FMR2.PLB) is activated the received 192 bits of payload data is looped back to the transmit direction. The framing bits, CRC6 ...
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Local Loop The local loopback mode, selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface are routed through the ...
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Single Channel Loop Back (loopback of time slots) The channel loopback is selected via LOOP.ECLB = 1. Each of the 24 time slots may be selected for loopback from the system PCM input (XDI) to the system PCM output ...
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Alarm Simulation (T1/J1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible “real“ alarm conditions are not reported to the processor or to the remote end when ...
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Operational Description E1 6.1 Operational Overview E1 ® The FALC -LH in principle can be operated in two modes, which are either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte or ...
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Table 39 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning LOOP 00 H XSW 40 H XSP 00 H TSWM 00 H XC0 00 H XC1 9C H RC0 00 H RC1 9C H IDLE 00 H ICB ...
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The bit FMR1.PMOD should always be kept low (otherwise T1/J1 mode is selected). Table 40 Initialization Parameters (E1) Basic Set Up Mode Select Specification of Line interface and clock generation Line interface ...
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Table 41 Line Interface Initialization (E1) Register Function FMR0.XC0 The FALC FMR0.RC0 interface as well as the digital line interface. For the analog line LIM1.DRS interface the codes AMI and HDB3 are supported. For the digital FMR3.CMI line interface ...
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Table 42 Framer Initialization (E1) (cont’d) Register Function FMR2.ALMF = 1 The receiver initiates a new basic- and multiframing research if more than 914 CRC4 errors have been detected in one second. FMR2.FRS1 the interworking mode the ...
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Operational Description T1/J1 7.1 Operational Overview T1/J1 ® The FALC -LH in principle can be operated in two modes, which are either E1 mode or T1/J1 mode. There are only minor differences between T1 and J1 mode which are ...
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Table 45 Initial Values after reset and FMR1.PMOD = 1 (T1/J1) Register Initiated Value FMR0 00 H FMR1 10 H FMR2 00 H SIC1 00 H SIC2 SIC3 00 H LOOP 00 H FMR4 00 H FMR5 ...
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T1/J1 Initialization For a correct start up of the Primary Access Interface a set of parameters specific to the system and hardware environment must be programmed after pin RES goes inactive (low). Both the basic and the operational parameters must ...
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Note: Read access to unused register addresses: value should be ignored. Write access to unused register addresses: should be avoided, or set to ‘00’hex. All control registers (except XFIFO, XS1-12, CMDR, DEC) are of type: Read/Write Specific T1/J1 Initialization The ...
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Table 48 Framer Initialization (T1/J1) (cont’d) Register 1) RCO.SJR = 1 FMR0.SRAF = 0 XSW.XRA = 1 1) RCO.SJR = 0 CRC6 calculation without FS/DL bits 1) RCO.SJR = 1 FMR4.AUTO = 1 Automatic synchronization in case of definite framing ...
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Table 50 Initialization of the CAS-BR Controller (T1/J1) Register Function FMR5.EIBR = 1 Enable CAS-BR Mode FMR1.SIGM = 1 Send CAS-BR information stored in XS1...12 IMR1.CASE = 0 Enable interrupts which indicate the access to the XS1...12 CAS- IMR0.RSC = ...
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Signaling Controller Operating Modes The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can ...
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Transparent Mode 0 (MODE.MDS2...0 = 100) Characteristics: FLAG and CRC generation/check, bit-stuffing No address recognition is performed and each frame is stored in the RFIFO. 8.1.4 Receive Data Flow The following figure gives an overview of the management of ...
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Transmit Data Flow The frames can be transmitted as shown below. FLAG Transmit HDLC Frame (XHF) Figure 57 HDLC Transmit Data Flow of FALC Transmitting a HDLC frame via register CMDR.XHF, the address, the control fields and the data ...
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Signaling Controller Functions 8.3.1 Shared Flags The closing Flag of a previously transmitted frame simultaneously becomes the opening Flag of the following frame if there is one to be transmitted. The Shared Flag feature is enabled by setting bit ...
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After having written bytes to XFIFO, the command XREP and XTF via the CMDR register (bit ‘00100100’ XFIFO repeatedly to the remote end. Note: The cyclic transmission continues until a reset ...
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XFIFO, i.e. a 32-byte pool is accessible to the CPU. This process is repeated until the CPU indicates the end of message by XME command, after which frame transmission is finished ...
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System Interface R FALC CPU Interface WR XFIFO 32 bytes Figure 59 Interrupt Driven Transmission Example 8.3.8 HDLC Data Reception 2 32 byte FIFO buffers are also provided in receive direction. There are different interrupt indications concerned with the ...
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S bit Access (E1) a ® The FALC -LH supports the S • access via registers RSW/XSW • access via registers RSA8-4/XSA4-8 • capable of storing the information for a complete multiframe the access via the 64 byte deep ...
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Byte sampling in BOM Mode (T1/J1) a) 1111 1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111 sync not stored b) 1111 1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111 ...
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Data Link Access in ESF/F72 Format (T1/J1) ® The FALC -LH supports the DL-channel protocol using the ESF or F72 (SLC96) format as follows: • Sampling of DL bits is done on a multiframe basis and stored in the ...
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Register Description Due to the different device function in E1 and T1/J1 mode, several registers and register bits have dedicated functions according to the selected operation mode. To maintain easy readability this chapter is divided into separate E1 and T1/J1 ...
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E1 Registers 9.1 E1 Control Register Addresses • Table 51 E1 Control Register Address Arrangement Address Register 00 XFIFO 01 XFIFO 02 CMDR 03 MODE 04 RAH1 05 RAH2 06 RAL1 07 RAL2 08 IPC 09 CCR1 0A CCR3 ...
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Table 51 E1 Control Register Address Arrangement (cont’d) Address Register 1B FMR1 1C FMR2 1D LOOP 1E XSW 1F XSP 20 XC0 21 XC1 22 RC0 23 RC1 24 XPM0 25 XPM1 26 XPM2 27 TSWM 29 IDLE 2A XSA4 ...
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Table 51 E1 Control Register Address Arrangement (cont’d) Address Register 3A LCR2 3B LCR3 3C SIC1 3D SIC2 3E LIM3 40 SIC3 60 DEC 70 XS1 71 XS2 72 XS3 73 XS4 74 XS5 75 XS6 76 XS7 77 XS8 ...
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Detailed Description of E1 Control Registers Transmit FIFO (Write) 7 XFIFO XF7 Writing data to XFIFO can be done in 8-bit (byte) or 16-bit (word) access. The LSB is transmitted first bytes/16 words of transmit data ...
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XRES… Transmitter Reset The transmit framer and transmit line interface including DCO-X are reset. However, the contents of the control registers is not deleted. XRES has to be given every time after a configuration change. XHF… Transmit HDLC Frame After ...
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Mode Register (Read/Write) Value after RESET MODE MDS2 MDS1 MDS2...0… Mode Select The operating mode of the HDLC controller is selected. 000… Reserved 001… Reserved 010… 1 byte address comparison mode (RAL1,2) 011… 2 byte address comparison ...
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Receive Address Byte High Register 2 (Read/Write) Value after RESET RAH2 RAH2… Value of Second Individual High Address Byte Receive Address Byte Low Register 1 (Read/Write) Value after RESET RAL1 RAL1… Value of First ...
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SCI… Status Change Interrupt 0 Interrupts ISR2.LOS, ISR2.AIS, ISR3.API and ISR3.LMFA16 are generated only on the rising edge of the corresponding status flag. 1 Interrupts ISR2.LOS, ISR2.AIS, ISR3.API and ISR3.LMFA16 are generated on the rising and falling edge of the ...
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CASM… CAS Synchronization Mode Determines the synchronization mode of the channel associated signaling multiframe alignment. 0… Synchronization is done in accordance to ITU-T G. 732 1… Synchronization is established when two consecutively correct multiframe alignment pattern are found. EITS… Enable ...
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Note seen that changing the value of RFT1 possible even RFT1 Common Configuration Register 3 (Read/Write) Value after RESET CCR3 PRE1 PRE0 Note: Unused bits have to be cleared. ...
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RADD… Receive Address Pushed to RFIFO If this bit is set, the received HDLC address information ( bytes, depending on the address mode selected via MODE.MDS0) is pushed to RFIFO. See description. RCRC… Receive CRC ON/OFF If this ...
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Receive Timeslot Register 1...4 (Read/Write) Value after RESET RTR1 TS0 TS1 RTR2 TS8 TS9 TS16 TS17 RTR3 RTR4 TS24 TS25 TS0…31… Timeslot Register These bits define the received time slots on the system highway port ...
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Transmit Timeslot Register 1...4 (Read/Write) Value after RESET TTR1 TS0 TS1 TTR2 TS8 TS9 TS16 TS17 TTR3 TTR4 TS24 TS25 TS0…31… Transmit Timeslot Register These bits define the transmit time slots on the system highway ...
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Interrupt Mask Register 0...5 (Read/Write) Value after RESET IMR0 RME RFS IMR1 LLBSC RDO IMR2 FAR LFA IMR3 ES SEC IMR4 LFA FER IMR5 XSP XSN IMR0...IMR5... Interrupt Mask Register Each interrupt source can generate ...
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RC1...0… Receive Code Serial code for the receiver is independent to the transmitter. 00... NRZ (optical interface) 01... CMI (1T2B+HDB3), (optical interface) 10... AMI (ternary or digital dual rail interface) 11... HDB3 Code (ternary or digital dual rail interface) EXTD… ...
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SIM… Alarm Simulation 0… Normal operation. 1… Initiates internal error simulation of AIS, loss of signal, loss of synchronization, remote alarm, slip, framing errors, CRC errors, and code violations. The error counters FEC, CVC, CEC1 are incremented. Framer Mode Register ...
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PMOD… PCM Mode For E1 application this bit must be set low. Switching from vice versa the device needs settle up to the internal clocking. 0… PCM mode. ...
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Framer Mode Register 2 (Read/Write) Value after RESET FMR2 RFS1 RFS0 RFS1... 0... Receive Framing Select 00… Doubleframe format 01… Doubleframe format 10… CRC4 Multiframe format 11… CRC4 Multiframe format with modified CRC4 Multiframe alignment algorithm (Interworking ...
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With XSP.TT0=1 timeslot 0 is also looped. If XSP.TT0=0 timeslot 0 is generated internally. AIS is sent immediately on port RDO by setting the FMR2.SAIS bit recommended to write the actual value of XC1 into this register ...
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Channel Loop Back Register (Read/Write) Value after RESET LOOP SPN SFM SPN… Select Additional Optical Pin Functions Together with bit LIM3.ESY the functionality of pin 80 is defined: Programming of LOOP.SPN and LIM3.ESY and the corresponding pin ...
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ECLB… Enable Channel Loop Back 0... Disables the channel loop back. 1... Enables the channel loop back selected by this register. CLA4...0… Channel Address For Loop Back CLA = 0…31 selects the channel. During looped back the contents of the ...