MT18HTS25672RHZ-80EH1 Micron Technology Inc, MT18HTS25672RHZ-80EH1 Datasheet

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MT18HTS25672RHZ-80EH1

Manufacturer Part Number
MT18HTS25672RHZ-80EH1
Description
MODULE DDR2 SDRAM 2GB 200SORDIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet

Specifications of MT18HTS25672RHZ-80EH1

Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
800MT/s
Features
-
Package / Case
200-SORDIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
DDR2 SDRAM SORDIMM
MT18HTS25672RHZ – 2GB
Features
• 200-pin, small-outline registered dual in-line memo-
• Fast data transfer rates: PC2-4200, PC2-5300, or
• 2GB (256 Meg x 72)
• Supports ECC error detection and correction
• V
• V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent opera-
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Phase-lock loop (PLL) to reduce system clock line
• Gold edge contacts
• Dual rank, using 2Gb TwinDie™ devices
• Halogen-free
• Combination Temp Sensor/EEPROM
Table 1: Key Timing Parameters
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
ry module (SORDIMM)
PC2-6400
tion
loading
Speed
Grade
DD
DDSPD
-80E
-800
-667
-53E
-40E
= 1.8V
= 3.0–3.6V
Products and specifications discussed herein are subject to change by Micron without notice.
Nomenclature
Industry
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
t
CK
CL = 6
800
800
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
CL = 5
Data Rate (MT/s)
800
667
667
1
Figure 1: 200-Pin SORDIMM (R/C B)
Module height: 30mm (1.181 in)
CL = 4
Options
• Operating temperature
• Package
• Frequency/CL
533
533
553
553
400
Notes:
– Commercial (0°C ≤ T
– Industrial (–40°C ≤ T
– 200-pin DIMM (Halogen-free)
– 2.5 @ CL = 5 (DDR2-800)
– 2.5 @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1. Contact Micron for industrial temperature
2. CL = CAS (READ) latency; registered mode
CL = 3
400
400
400
400
400
module offerings
will add one clock cycle to CL.
2
t
(ns)
12.5
RCD
15
15
15
15
A
A
≤ +85°C)
≤ +70°C)
© 2010 Micron Technology, Inc. All rights reserved.
1
(ns)
12.5
t
15
15
15
15
RP
Features
Marking
None
-80E
-800
-667
(ns)
t
55
55
55
55
55
Z
RC
I

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MT18HTS25672RHZ-80EH1 Summary of contents

Page 1

... DDR2 SDRAM SORDIMM MT18HTS25672RHZ – 2GB Features • 200-pin, small-outline registered dual in-line memo- ry module (SORDIMM) • Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400 • 2GB (256 Meg x 72) • Supports ECC error detection and correction • 1.8V DD • 3.0–3.6V DDSPD • ...

Page 2

... The data sheet for the base device can be found on Micron’s Web site. Notes: 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672RHZ-80EG1. PDF: 09005aef83f287c1 hts18c256x72rhz.pdf - Rev. A 3/10 EN ...

Page 3

Pin Assignments Table 4: Pin Assignments 200-Pin SORDIMM Front Pin Symbol Pin Symbol Pin DQ18 101 REF 3 DQ0 53 DQ19 103 105 DQ1 57 DQ24 107 9 DQS0# 59 ...

Page 4

... Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 5: Pin Descriptions Symbol Type Ax Input BAx Input ...

Page 5

Table 5: Pin Descriptions (Continued) Symbol Type SDA I/O RDQSx, Output RDQS#x Err_Out# Output (open drain Supply DD DDQ V Supply DDSPD V Supply REF V Supply SS – NC – NF – NU – RFU PDF: 09005aef83f287c1 ...

Page 6

Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1# DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 ...

Page 7

... DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans- fers at the I/O pins. DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals ...

Page 8

Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in the device data ...

Page 9

... Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Mi- cron encourages designers to simulate the signal characteristics of the system's memo- ry bus to ensure adequate signal integrity of the entire memory system ...

Page 10

IDD Specifications Table 8: DDR2 I Specifications and Conditions – 2GB DD Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter Operating one bank ...

Page 11

Table 8: DDR2 I Specifications and Conditions – 2GB (Continued) DD Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter Operating bank interleave read ...

Page 12

Register and PLL Specifications Table 9: Register Specifications SSTU32872 devices or equivalent Parameter Symbol DC high-level V Control, command, IH(DC) input voltage DC low-level V Control, command, IL(DC) input voltage AC high-level V Control, command, IH(AC) input voltage AC low-level ...

Page 13

Table 10: PLL Specifications CUA845 device or JEDEC82-21 equivalent Parameter Symbol DC high-level V IH input voltage DC low-level V IL input voltage Input voltage (limits Input differential-pair V IX cross voltage Input differential volt- V ID(DC) age ...

Page 14

Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module’s temperature and can be read back at any time over the I Table 12: Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions Parameter/Condition Supply voltage Supply current: ...

Page 15

The interrupt mode enables software to reset EVENT# after a critical temperature thresh- old has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and ...

Page 16

Figure 3: EVENT# Pin Functionality Critical Alarm window (MAX) Alarm window (MIN) EVENT# interrupt mode EVENT# comparator mode EVENT# critical temperature only mode Table 14: Temperature Sensor Registers Name Pointer register Capability register Configuration register Alarm temperature upper boundary register ...

Page 17

Table 15: Pointer Register Bits 0– Table 16: Pointer Register Bits 0–2 Descriptions Capability Register The capability register indicates the features and functionality supported by the temper- ature sensor. ...

Page 18

Table 18: Capability Register Bit Description (Continued) Bit Description 4:3 Temperature resolution 00: 0.5°C LSB 01: 0.25°C LSB 10: 0.125°C LSB 11: 0.0625°C LSB 15:5 0: Must be set to zero Configuration Register Table 19: Configuration Register (Address: 0x01) 15 ...

Page 19

Table 20: Configuration Register Bit Descriptions (Continued) Bit Description 6 Alarm window lock bit 0: Alarm trips are not locked and can be changed 1: Alarm trips are locked and cannot be changed 7 Critical trip lock bit 0: Critical ...

Page 20

Figure 4: Hysteresis Applied to Temperature Around Trip Points Below window bit Above window bit 1. T Notes Hyst is the value set in the hysteresis bits of the configuration register. Table 21: Hysteresis Applied to Alarm ...

Page 21

Temperature Trip Point Registers The upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in the register will always report zero. ...

Page 22

Table 25: Temperature Register (Address: 0x05 Above Above Below MSB critical alarm alarm trip window window Table 26: Temperature Register Bit Descriptions Bit Description 13 Below alarm window 0: Temperature is equal to or above the lower ...

Page 23

Module Dimensions Figure 5: 200-Pin DDR2 SORDIMM 2.0 (0.079) R (2X) U1 1.0 (0.039) R (2X) 1.8 (0.071) (2X) 6.0 (0.236) TYP 2.0 (0.079) TYP 45° 3.5 (0.138) TYP Pin 200 1.0 (0.039) TYP 1. All dimensions are ...

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