HD64570F16 Renesas Electronics America, HD64570F16 Datasheet
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HD64570 SCA Serial Communications Adaptor ADE-602-035B Rev. 3.0 August 28, 1998 Hitachi Company or Division User’s Manual ...
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Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with ...
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The HD64570 serial communications adaptor (SCA) peripheral chip enables a host microprocessor to perform asynchronous, byte-synchronous, or bit-synchronous serial communication. Its two full-duplex, multiprotocol serial channels support a wide variety of protocols, including frame relay, LAPB, LAPD, bisync, and ™DDCMP. ...
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Changes in the Revised Edition The following tables list the main differences between this revision and the previous edition (ADE-602-035A). (2nd edition) The changes are marked with stars (*) in the text. Changes in the Specifications Specifications WTR SCA added ...
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How to Use This Manual This user's manual describes the functions, performance, and usage of the HD64570 serial communications adaptor (SCA general-purpose communications control chip. This manual consists of eleven chapters and an appendix. — Section 1 Overview ...
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Section 9 Application Examples This section shows examples of software routines and circuits in some typical applications of the SCA. — Section 10 Electrical Specifications This section lists the SCA's electrical characteristics (absolute maximum ratings, DC characteristics, AC characteristics) ...
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Use the following flowchart as a guide to reading this manual. Start Want a general overview of the SCA? No Want to see a list of registers? No Want to see block diagrams of modules? No Want to see pin ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Features.............................................................................................................................. 1.3 Basic Functions.................................................................................................................. 1.4 Block Diagram................................................................................................................... 1.5 Protocol Support................................................................................................................ 1.5.1 Asynchronous Mode ............................................................................................ 1.5.2 Byte-Synchronous Mode...................................................................................... 1.5.3 Bit-Synchronous Mode ........................................................................................ 1.6 Built-In Registers............................................................................................................... 1.6.1 Low-Power Mode Control Registers.................................................................... 10 1.6.2 Interrupt Control ...
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Section 3 System Controller 3.1 Overview............................................................................................................................ 55 3.2 Chip Operating Modes ...................................................................................................... 55 3.2.1 SCA Operating Modes ......................................................................................... 55 3.2.2 Low-Power Register (LPR).................................................................................. 57 3.2.3 Reset Mode........................................................................................................... 58 3.2.4 Normal Operating Mode ...................................................................................... 60 3.2.5 System Stop Mode................................................................................................ 60 3.3 ...
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MSCI RX Clock Source Register (RXS) ............................................................. 121 5.2.6 MSCI TX Clock Source Register (TXS).............................................................. 123 5.2.7 MSCI Time Constant Register (TMC) ................................................................. 125 5.2.8 MSCI Command Register (CMD)........................................................................ 126 5.2.9 MSCI Status Register 0 (ST0).............................................................................. 131 5.2.10 MSCI ...
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Interrupt Enable Conditions ................................................................................. 237 5.8 Reset Operation ................................................................................................................. 237 Section 6 Direct Memory Access Controller (DMAC) 6.1 Overview............................................................................................................................ 239 6.1.1 Functions .............................................................................................................. 239 6.1.2 Configuration and Operation................................................................................ 240 6.2 Registers ............................................................................................................................ 241 6.2.1 Channels 0, 2: Destination Address ...
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Timer up-counter (TCNT: TCNTH, TCNTL) .................................................... 304 7.2.2 Timer Constant Register (TCONR: TCONRH, TCONRL)................................ 305 7.2.3 Timer Control/Status Register (TCSR) ................................................................ 306 7.2.4 Timer Expand Prescale Register (TEPR) ............................................................. 307 7.3 Operation Timing .............................................................................................................. 308 7.3.1 Timer Increment Timing ...
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... AC Characteristics................................................................................................ 343 10.2 Electrical Characteristics of HD64570CP16 and HD64570F16 ....................................... 353 10.2.1 Absolute Maximum Ratings................................................................................. 353 10.2.2 DC Characteristics................................................................................................ 354 10.2.3 AC Characteristics................................................................................................ 355 10.3 Electrical Characteristics of HD64570CP8I and HD64570F8I......................................... 365 10.3.1 Absolute Maximum Ratings................................................................................. 365 10.3.2 DC Characteristics................................................................................................ 366 10.3.3 AC Characteristics................................................................................................ 367 10.4 Timing Diagrams ............................................................................................................... 377 10 ...
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Section 1 Overview 1.1 Overview The HD64570 serial communications adaptor (SCA) converts parallel data to serial data for communication with other devices. Its two independent, full-duplex transceivers support both synchronous (bit-synchronous or byte-synchronous) and asynchronous communication. Extensive protocol functions are ...
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Basic Functions Table 1.1 Major Functions of the SCA Item MSCI (multiprotocol Maximum data transfer serial communication rate interface) Number of channels Operating modes Protocol functions Error detection Transmission codes FIFO Clock sources Modem control ADPLL (Advanced digital PLL) ...
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... Product lineup Type Product Number SCA HD64570CP HD64570F High Speed HD64570CP1616.7 MHz + SCA HD64570F16 WTR SCA HD64570CP8I 8 MHz HD64570F8I Specification DMA transfer between memory and on-chip MSCI: 1. Single block transfer (asynchronous, byte-synchronous, bit- synchronous modes) 2. Chained-block transfer (bit-synchronous mode) 3 clocks 16 bits 1 ...
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Block Diagram Inter- INT rupt con- INTA troller HOLD/BUSREQ Bus HOLDA/BUSACK Arbi- BUSY ter BEO Wait WAIT con- troller CS WR R/W / RD/N.C. Bus AS inter- BHE/HDS face A /LDS ...
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Figure 1.2 MSCI Block Diagram Rev. 0, 07/98, page 5 of 453 ...
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DAR (24) BAR SAR (24) CPB (8) Reserved CDA (16) EDA (16) BFL (16)* BCR (16) Comparator (16) Incrementer/ decrementer (24) * Channels 0 and 2 only Figure 1.3 DMAC Block Diagram (one channel) Rev. 0, 07/98, page 6 of ...
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Clock Timer constant Timer up- register counter (TCONR) (TCNT) Comparator T0IRQ T1IRQ T2IRQ T3IRQ Figure 1.4 Timer Block Diagram Internal data bus Timer expand prescale register (TEPR) — — — — — 8 Counter reset CMF ECMI — TME — ...
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Physical address boundary register 0 (PABR0) Physical address boundary register 1 (PABR1) WAIT line Figure 1.5 Wait Controller Block Diagram 1.5 Protocol Support 1.5.1 Asynchronous Mode Item Character length Parity Stop bits Transmit/receive clock Error detection Break signal Break detection ...
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Byte-Synchronous Mode Item Character length Error control Synchronous characters External synchronization Synchronization Underrun Idle Error detection 1.5.3 Bit-Synchronous Mode Item Character length Error control Bit pattern Frame subdivision Address field End of frame Data input/output Residual bits Short frame ...
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Built-In Registers 1.6.1 Low-Power Mode Control Registers CPU Modes Register Name Symbol 0 & 1 Low power register LPR 00H 1.6.2 Interrupt Control Registers Register Name Symbol Channel 0 Interrupt vector IVR 1AH register Interrupt modified IMVR 1CH vector ...
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MSCI Registers (1) CPU Modes 0 & 1 Register Name Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB Mode register 0 MD0 2EH Mode register 1 MD1 2FH Mode register 2 MD2 30H Control register CTL 31H ...
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MSCI Registers (2) CPU Modes 0 & 1 Register Name Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB TX/RX buffer register TRBL 20H TRBH 21H RX ready control register RRC 3AH TX ready control register 0 TRC0 ...
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DMA Registers Provided Separately for Channels CPU Modes 0 & 1 Register Chan- Chan- Chan- Name Symbol nel 0 nel 1 nel 2 Destination DARL 80H A0H C0H address (BARL) register L (buffer address 1 register ...
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DMA Registers Provided Separately for Channels (cont) CPU Modes 0 & 1 Register Chan- Chan- Chan- Name Symbol nel 0 nel 1 nel 2 Current CDAH 89H A9H C9H descriptor address register H Error EDAL 8AH ...
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Timer Registers CPU Modes 0 & 1 Register Chan- Chan- Chan- Name Symbol nel 0 nel 1 nel 2 Timer up- TCNTL 60H 68H 70H counter TCNTH 61H 69H 71H Timer TCONRL 62H 6AH 72H constant register TCONRH 63H ...
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General Description of Functions 1.7.1 Operating Modes of Serial Section The normal SCA operating mode is full duplex (figure 1.6). The SCA can transmit and receive simultaneously, using two separate lines. In auto echo mode (figure 1.6), the SCA ...
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Mark Start bit Byte synchronous Bisync Header (arbitrary number of 8 bit characters) DDCMP Header Count Flag Acknow- (14 bits) (2 bits) ledge (8 bits) Bit synchronous LAPB Address Control Flag field field (8 bits) (8 bits) (8 bits) 01111110 ...
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Transmission Error Detection The SCA flags the following transmission errors in its status registers (ST1 and ST2) to notify the host MPU: 1. Parity error (asynchronous) This error occurs when the designated parity condition is not satisfied. It indicates ...
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Transmission Codes The SCA supports five transmission codes: NRZ, NRZI, FM0, FM1, and Manchester (figure 1.8). See figures 5.39, 5.40, and 5.41 for the timing relationships between the TX and RX clocks and each code. Type No. Code NRZ ...
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Transmit/Receive Clock Selection MSCI channels 0 and 1 in the SCA are full-duplex transceivers that support asynchronous, byte- synchronous, and bit-synchronous transmission formats. The transmit clock (figure 1.9) can be selected independently on each channel. The selectable clock sources ...
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RXC Line input RXCS2 to RXCS0 (RXS bits 111 ADPLL ADPLL clock clock selector 010 110 Baud rate generator (for receiving) Figure 1.10 Receive Clock Source Receive clock selector 000 (1/1, 1/16*, 1/32*, or 1/64* Receive clock ...
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... Same maximum transfer rate when receive clock noise is suppressed 4. Depends on setting of MSCI mode register 1 (MD1) 5. SCA (HD64570CP, HD64570F 2.5 (clock mode (clock mode 1.4 (clock mode) 10. High-speed SCA (HD64570CP16, HD64570F16) Rev. 0, 07/98, page 22 of 453 Maximum Transfer Rate (bps) Sampling Clock: External* External 4 Clock BRG 62.5k* 78 ...
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Transmitter The transmitter (figure 1.11) loads parallel data supplied from the data bus into a transmit FIFO consisting of 32 eight-bit registers. Next, according to the selected transmission format, it moves the data into a transmit shift register which ...
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Receiver The receiver (figure 1.13) converts serial receive data into parallel data according to the selected communication format. The LSB of the data is received first. The data are shifted through a succession of receive shift registers, the last ...
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From transmitter (local loop back) Zero deletion, flag, abort, or idle detection Receive data RXD Decoder Receive shift (1) register 1 (8) RXC ADPLL Receive clock RXC Baud rate generator To transmitter (local loop back and auto echo) TRB: TX/RX ...
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DMAC The DMAC module in the SCA has four independent channels (figure 1.14). The DMAC is used exclusively for single-address transfer between memory and the MSCI. Data can be transferred a word at a time or a byte at ...
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Memory Get bus Access memory 1. Put address on bus ( BHE active 3. RD active Send data 1. Decode address 2. Put data on bus 3. WAIT inactive End of transfer AS and RD ...
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Memory Access memory 1. Put address on bus ( BHE active Store data 1. Decode address 2. Write data 3. WAIT inactive End of transfer AS and WR inactive End of cycle WAIT active Relinquish ...
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Memory Get bus Access memory 1. Put address on bus ( active 3. RD active Send data 1. Decode address 2. Put data on bus 3. WAIT inactive End of transfer AS and RD inactive ...
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Memory Access memory 1. Put address on bus ( active Store data 1. Decode address 2. Write data 3. WAIT inactive End of transfer AS and WR inactive End of cycle WAIT active Relinquish bus ...
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Memory DMAC Get bus Access memory 1. Select read with R/W 2. Put address on bus ( active 4. HDS or LDS active Send data 1. Decode address 2. Put data on bus 3. WAIT ...
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Memory Access memory 1. Select write with R/W 2. Put address on bus ( active Store data 1. Decode address 2. Write data 3. WAIT inactive End of transfer AS, HDS, and LDS inactive End ...
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DMA Buffer Chaining In bit-synchronous mode, each DMAC channel in the SCA can perform chained-block transfer, in which one or more data blocks are transferred in a continuous sequence (figure 1.21). To set up a chained-block transfer: 1. Create ...
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Descriptor Structure Figure 1.22 shows the structure of a descriptor. Descriptors are allocated in memory in different ways, depending on the CPU mode. Address Bit ...
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Bus Arbiter The SCA has a built-in bus arbiter for arbitrating the bus between the on-chip DMAC and an external bus master device. This bus arbiter provides an easy way to design a multi-channel system using two or more ...
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Interrupt Control SCA interrupts are controlled by three interrupt status registers (ISR0, ISR1, ISR2) containing flags for 20 interrupt sources, three interrupt enable registers (IER0, IER1, IER2) which can mask the interrupt source flags individually, and one interrupt control ...
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Interrupt status register 0 (ISR0) TXINT1 RXINT1 MSCI TXRDY1 (channel 1) RXRDY1 TXINT0 RXINT0 TXRDY0 RXRDY0 MSCI Interrupt enable register 0 (IER0) (channel 0) TXINT1E RXINT1E TXRDY1E RXRDY1E TXINT0E RXINT0E DMAC TXRDY0E (channel 3) RXRDY0E Interrupt status register 1 (ISR1) ...
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MSCI status UDRN register 1 (ST1) IDL CLMD SYNCD/FLGD CCTS CDCD BRXD/ABTD BRXE/IDLD MSCI interrupt UDRNE enable register 1 IDLE (IE1) CLMDE SYNCDE/FLGDE CCTSE CDCDE BRXDE/ABTDE BRXEE/IDLDE MSCI status EOM register 2 (ST2) PMP/SHRT PE/ABT FRME/RBIT OVRN CRCE — — ...
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DMA status register (DSR) EOT EOM BOF COF — — DE DWE EOTE EOME BOFE COFE — — — — DMA interrupt enable register (DIR) Figure 1.26 Logic Flow for Interrupt Requests, Status, and Enable Bits in DMAC Module CMF ...
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Timers The SCA has a built-in four-channel, 16-bit timer module. All channels have identical functions and specifications. They can be used as interval timers or watchdog timers, or for time-out detection or other purposes. The timer features are listed ...
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Section 2 Pin Arrangements and Functions 2.1 Pin Arrangements Figures 2.1 and 2.2 show the pin arrangements of the SCA chip in QFJ (PLCC (CP-84)) and QFP (FP-88) packages, respectively. Bus interface ...
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N. SYNC1 69 RTS1 70 DCD1 71 Serial CTS1 72 I/O RxD1 73 channel 1 RxC1 74 TxC1 75 TxD1 SYNC0 RTS0 80 Serial DCD0 81 I/O CTS0 ...
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Pin Functions The function of each signal line is described below. Note that permanent or temporary input lines must never be left unconnected. Table 2.1 Power Supply Pin Number Symbol CP-84 FP-88 V 21, 22, 44, 65, 10, 33, ...
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Table 2.4 Address Lines Pin Number Symbol CP-84 FP- 18, 20, 28 30, 32 44, 46 22, 24 27Input Rev. 0, 07/98, page 44 ...
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Table 2.5 Data Lines Pin Number Symbol CP-84 FP *1: Not connected Input/ Output Description Input/ Data bus: ...
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Table 2.6 Bus Interface Lines Pin Number Symbol CP-84 FP-88 RD WR/ *2: Not connected Rev. 0, 07/98, page 46 of 453 Input/ Output Description Input/ CPU modes 0, 1 output Read: Indicates that the ...
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Table 2.6 Bus Interface Lines (cont) Pin Number Symbol CP-84 FP-88 WR/R /LDS Input/ Output Description Input/ Master mode Output line. When this line is output driven high, data moves in the input direction. ...
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Table 2.6 Bus Interface Lines (cont) Pin Number Symbol CP-84 FP-88 BHE/HDS *1: Not connected Rev. 0, 07/98, page 48 of 453 Input/ Output Description Input/ CPU mode 0 output Bus high enable: High-order ...
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Table 2.6 Bus Interface Lines (cont) Pin Number Symbol CP-84 FP-88 WAIT 81 8 Input/ Output Description Input/ Wait: Used to extend read and write cycles. output CPU mode 0 Master mode If this line is high at the rising ...
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Table 2.6 Bus Interface Lines (cont) Pin Number Symbol CP-84 FP- Rev. 0, 07/98, page 50 of 453 Input/ Output Description Input/ Address strobe: Indicates whether the address output bus is active. CPU modes 0,1 Master mode ...
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Table 2.7 System Control Lines Pin Number Symbol CP-84 FP-88 HOLD BUSREQ HOLDA BUSACK BEO 79 6 Input/ Output Description Output CPU mode 0 Hold: Used to request the bus. By driving HOLD active high, the ...
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Table 2.7 System Control Lines (cont) Pin Number Symbol CP-84 FP-88 BUSY 80 7 CPU0, 74, 73 88, 87 CPU1 Note: Do not change the mode when the SCA is turned on. Rev. 0, 07/98, page 52 of 453 Input/ ...
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Table 2.8 Interrupt Lines Pin Number Symbol CP-84 FP-88 INT 75 2 INTA 76 3 Note signal is input on this line in non-acknowledge mode, pull this line Table 2.9 Serial I/O (MSCI) Lines There ...
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Table 2.9 Serial I/O (MSCI) Lines (cont) Pin Number Symbol CP-84 FP-88 RTS0, 66, 56 80, 70 RTS1 DCD0, 67, 57 81, 71 DCD1 CTS0, 68, 58 82, 72 CTS1 SYNC0, 64, 55 78, 69 SYNC1 Note: For details concerning ...
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Section 3 System Controller 3.1 Overview Features of the SCA's system controller: Three chip operating modes Reset mode Normal operating mode System stop mode An on-chip bus arbiter arbitrates bus contention between the external bus master and on-chip DMA controller ...
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Reset mode Note: IOSTP is bit 0 in the low power register (LPR). Figure 3.1 Chip Operating Mode Transitions Table 3.1 indicates the operational status of the main functional modules in each of the operating modes. Table 3.1 Operational Status ...
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Bit name — Read/Write — Initial value 0 Note: Bit 7–bit 1 are reserved. These bits always read 0 and must be set to 0. Bits 7 1: Reserved. These bits always read 0 and must be set to ...
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Reset Mode Holding the RESET line low for six or more clock cycles resets all SCA functional modules and puts the SCA into reset mode. In this mode, the SCA operates as follows: The MSCI, DMAC, and timers halt, ...
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CLK (CPU modes CLK (CPU mode 0) 6 clock cycles or more RESET RD WR/R/W A /LDS 0 BHE/HDS WAIT AS BUSY ...
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From the normal operating mode it is possible to enter any other chip operating mode, as follows: If the RESET signal is active for six clock cycles or more, the SCA enters reset mode. If the IOSTP bit is set ...
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System stop mode is released when the RESET signal becomes active for six clock cycles or more, placing the SCA in reset mode. CLK BHE Normal operating mode ...
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CLK HDS, LDS R Normal operating mode CLK HDS, LDS R Normal operating mode Figure 3.3 ...
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Table 3.2 Signal Line States in System Stop Mode Signal Line CPU Mode Input High impedance 8 23 BUSY Input BEO High output RD/NC Input WR/R/W Input A /LDS Input 0 BHE/HDS Input ...
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Figure 3.4 shows the interconnections of the bus arbiter and bus masters. DMAC arbiter Figure 3.4 Bus Arbiter and Bus Masters 3.3.2 Timing for Passing Bus Control If BUSACK becomes inactive (high) (HOLDA becomes low in CPU mode 0) during ...
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RESET = 0 *2 Reset mode Notes: 1. See section 6, DMAC for information about DMA requests. If the RESET signal is driven active low for six cycles or more, the SCA 2. unconditionally enters reset mode. When RESET goes ...
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SCA slave mode and is an output in master mode.) When the SCA detects BUSACK low and if no other bus master is using the bus, that is, BUSY is high, the SCA acquires control of the ...
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In this sequence, after driving BUSREQ active, the SCA samples the BUSACK input from the master MPU and the BUSY input from the other bus master at each rising edge of CLK. When the SCA detects BUSACK low and BUSY ...
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CLK (CPU modes CLK (CPU mode 0) BUSREQ (CPU modes HOLD (CPU mode 0) BUSACK (CPU modes HOLDA (CPU mode 0) Input BUSY BEO Slave mode CLK (CPU modes 1, 2, ...
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CLK (CPU modes CLK (CPU mode 0) BUSREQ (CPU modes HOLD (CPU mode 0) BUSACK (CPU modes HOLDA (CPU mode 0) Input BUSY BEO Slave mode Figure 3.6 Bus Arbitration Sequence ...
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Bus Interface 3.4.1 Overview The SCA has four 8- and 16-bit bus interfaces that can be switched under external control. The bus interface is selected according to the CPU mode as shown in table 3.3. Table 3.3 CPU Mode ...
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MPU BHE Odd-address Even-address memory bank memory bank Figure 3.8 Data Bus Mapping onto Memory Banks in CPU Modes 0, 2, ...
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CLK BHE Register address WAIT (Out (In) Read cycle SCA Note states are required between successive ...
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CPU Mode 1: The SCA latches the address on lines A must remain low throughout the bus cycle. After the bus cycle ends, CS must go high (inactive). Figure 3.10 shows the slave mode bus timing sequence in CPU mode ...
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Read cycle When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T T states, the SCA outputs the contents of the register specified by the address on the data bus 3 ...
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Read cycle When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T T states, the SCA outputs the contents of the register specified by the address on the data bus 2 ...
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Master Mode Bus Cycle In master mode (DMA mode), data moves from memory to the SCA in a read cycle, and from the SCA to memory in a write cycle. The address and bus interface signals are output signals, ...
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Transfer of Three or More Bytes from Odd Address: In CPU modes 0, 2, and 3, to transfer three or more bytes starting at an odd address by direct memory access, the DMAC first transfers one byte from the odd ...
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DMA read cycle T 1 CLK BHE Memory address (ME) WAIT (Out (In) DMA read cycle CLK BHE ...
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DMA read cycle CLK Memory address (ME) WAIT (Out (In) Data latch point No T DMA read cycle ...
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T CLK HDS, LDS WAIT R (Out (In) DMA read cycle CLK Memory address HDS, ...
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Section 4 Interrupt Controller 4.1 Overview The SCA has a single INT signal line for sending interrupt requests to a host MPU. The INT signal is generated by 20 interrupt sources on the SCA chip. Figure 4.1 shows the location ...
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Table 4.1 lists the interrupts in priority order and names of their sources. Table 4.1 Interrupt Priority and Interrupt Sources Module Interrupt Name MSCI0 RXRDY0 MSCI0 TXRDY0 MSCI0 RXINT0 MSCI0 TXINT0 MSCI1 RXRDY1 MSCI1 TXRDY1 MSCI1 RXINT1 MSCI1 TXINT1 DMAC0 ...
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Registers The SCA has nine registers for interrupt control. These registers can be accessed by read and write instructions from the MPU. 4.2.1 Interrupt Vector Register (IVR) The interrupt vector register stores the vector address output to the MPU ...
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Bit name IMVR7 IMVR6 Read/Write R/W Initial value 0 Note: The codes generated for each interrupt source are listed in table 4.2. Bits 7 and 6 are cleared reset. Bits always read ...
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Bit 7 (IPC: Interrupt Priority Control): Controls the priority order of interrupt sources. This bit is cleared reset. IPC = 0: MSCI interrupt sources have higher priority than DMAC interrupt sources. IPC = 1: DMAC interrupt ...
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Interrupt Status Register 0 (ISR0) The read-only interrupt status register 0 indicates the status of interrupt request sources. All bits are cleared reset Bit name TXINT1RXINT1TXRDY1 R XRDY1 Read/Write R R Initial value ...
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Bit 6 (RXINT1: MSCI Channel 1 RXINT): RXINT1 = 0: MSCI channel 1 is not requesting a RXINT interrupt. RXINT1 = 1: MSCI channel 1 is requesting a RXINT interrupt. Bit 5 (TxRDY1: MSCI Channel 1 TXRDY): TXRDY1 = 0: ...
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Interrupt Status Register 1 (ISR1) The read-only interrupt status register 1 indicates the status of interrupt request sources. All bits are cleared reset Bit name DMIB3 DMIA3 DMIB2 Read/Write R R Initial value ...
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Bit 6 (DMIA3: DMA Channel 3 Interrupt A): DMIA3 = 0: DMAC channel 3 is not requesting a DMIA interrupt. DMIA3 = 1: DMAC channel 3 is requesting a DMIA interrupt. Bit 5 (DMIB2: DMA Channel 2 Interrupt B): DMIB2 ...
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Interrupt Status Register 2 (ISR2) The read-only interrupt status register 2 indicates the status of interrupt request sources. Bits are cleared reset. Bits are reserved bits that always read ...
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Bit 7 (T3IRQ: Timer Channel 3 Interrupt Request): T3IRQ = 0: Timer channel 3 is not requesting a T3IRQ interrupt. T3IRQ = 1: Timer channel 3 is requesting a T3IRQ interrupt. Bit 6 (T2IRQ: Timer Channel 2 Interrupt Request): T2IRQ ...
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Interrupt Enable Register 0 (IER0) The interrupt enable register 0 enables or disables interrupt requests indicated in interrupt status register 0 (ISR0). All IER0 bits are cleared reset Bit name TXINT1E RXINT1E TXRDY1E ...
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Bit 6 (RXINT1E: MSCI Channel 1 RXINT Enable): RXINT1E = 0: The MSCI channel 1 RXINT interrupt is disabled. RXINT1E = 1: The MSCI channel 1 RXINT interrupt is enabled. Bit 5 (TXRDY1E: MSCI Channel 1 TXRDY Enable): TXRDY1E = ...
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Interrupt Enable Register 1 (IER1) The interrupt enable register 1 enables or disables interrupt requests indicated in interrupt status register 1 (ISR1). All IER1 bits are cleared reset Bit name DMIB3E DMIA3E DMIB2E ...
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Bit 6 (DMIA3E: DMA Channel 3 Interrupt A Enable): DMIA3E = 0: The DMAC channel 3 DMIA interrupt is disabled. DMIA3E = 1: The DMAC channel 3 DMIA interrupt is enabled. Bit 5 (DMIB2E: DMA Channel 2 Interrupt B Enable): ...
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Interrupt Enable Register 2 (IER2) The interrupt enable register 2 enables or disables interrupt requests indicated in interrupt status register 2 (ISR2). IER2 bits are cleared reset. Bits are ...
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Bit 5 (T1IRQE: Timer Channel 1 Interrupt Request Enable): T1IRQE = 0: The timer channel 1 T1IRQ interrupt is disabled. T1IRQE = 1: The timer channel 1 T1IRQ interrupt is enabled. Bit 4 (T0IRQE: Timer Channel 0 Interrupt Request Enable): ...
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Vector Output Two types of vectors can be selected for output from the SCA. The vector is output on data bus lines (The output on lines Fixed vector: An arbitrary 8-bit ...
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CLK (CPU mode 0) CLK (CPU modes INT INTA WAIT (Out) Figure 4.2 Timing Sequence of Single Acknowledge Cycle CLK (CPU mode 0) CLK (CPU modes INT INTA WAIT ...
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Interrupt Sources and Vector Addresses The interrupt modified vector register (IMVR eight-bit register in which the six low bits (bits hold a hardware-generated code identifying an interrupt source, as listed in table 4.2. The ...
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Section 5 Multiprotocol Serial Communication Interface 5.1 Overview The multiprotocol serial communication interface (MSCI) supports three different communication modes: asynchronous, byte synchronous, and bit synchronous. The two full-duplex channels of the MSCIs, built in the SCA, have identical functions but ...
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Programmable parity (odd, even parity) Detection of parity, overrun, and framing errors Break transmission and reception Multiprocessor (MP) bit transmission and reception Programmable bit rate (input clock frequency Byte Synchronous Mode 8-bit character length Mono-sync, bi-sync, and external ...
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MSCI Current Status Register 0 (CST0), and 5.2.26, MSCI Current Status Register 1 (CST1). Input data is received via the RXD line and enters the MSCI internal circuitry after passing through a decoder. The data path inside the ...
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TX shift register. The data is then output to the TXD line via the encoder. See sections 5.2.1, MSCI Mode Register 0 (MD0), 5.2.2, MSCI Mode Register 1 (MD1), 5.2.4, MSCI Control ...
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Async PRTCL2 PRTCL1 PRTCL0AUTO Byte sync Bit sync HDLC Read/Write R/W R Initial value Protocol mode Auto-enable 000: Asynchronous mode 0: 001: Byte-sync 1: mono-sync mode 010: Byte-sync Bi-sync mode 011: Byte-sync external synchronous mode 100: ...
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Asynchronous/Byte synchronous/Bit synchronous mode AUTO = 0: Specifies CTS and DCD as general-purpose inputs, and RTS as a general- purpose output. CTS, DCD, and RTS have no effect on MSCI transmission or reception AUTO = 1: Sets the auto-enable function. ...
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TXC TXD RTS (a) Auto-Enable, 5 Bits/Character, No Parity, and 1/1 Clock Mode MPU write cycle T1 T2 CLK WR RTS (b) CPU Mode 0, MPU Write Cycle Figure 5.1 Modem Control Signal Timing Write 1 to RTS bit T4 ...
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T1 CLK WR RTS T1 CLK HDS, LDS R/W RTS T1 CLK HDS, LDS R/W RTS Figure 5.1 Modem Control Signal Timing (cont) Rev. 0, 07/98, page 108 of 453 MPU write cycle (c) CPU Mode ...
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DMA read cycle CLK RD RTS (f) CPU Mode 0, DMA Read Cycle DMA read cycle CLK RD RTS (g) CPU Mode 1, DMA Read Cycle DMA read cycle T1 T2 CLK HDS, LDS ...
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Bit 3: Reserved. This bit always reads 0 and must be set to 0. Bit 2 (CRCCC: CRC Code Calculation): Specifies CRC code generation/detection in byte synchronous or bit synchronous mode. Asynchronous mode Reserved. This bit always reads 0 and ...
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CRC0 = 1: Specifies all 1s as the CRC calculator initial value The following CRC bit patterns are sent starting with the most significant bit. CRC-16 Protocol Preset 0 BOP (bit synchronous Complemented* mode) COP (byte Not synchronous mode) complemented ...
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BRATE1 BRATE0 TXCHR1 Async — * — * — Byte sync Bit sync HDLC ADDRS1 A DDRS0 Read/Write R/W R/W R/W Initial value Transmit character length Bit rate • Asynchronous mode • Asynchronous mode ...
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Bits 7 6 (BRATE1 BRATE0/ADDRS1 ADDRS0: Bit Rate/Address Field Check): Specify the relationship between the bit rate and the transmit/receive clock in asynchronous mode, and the checking method for the address field in bit synchronous mode. These bits are used ...
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RXCHR1, RXCHR0 = bits/character Byte synchronous/Bit synchronous mode Reserved. These bits always read 0 and must be set to 0. Bits 1 0 (PMPM1 PMPM0: Parity/Multiprocessor Mode): Specify the multiprocessor (MP) mode, and whether or not to ...
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Async Byte sync NRZFM CODE1 CODE0 Bit sync HDLC Read/Write R/W R/W R/W Initial value NRZ or FM select • Byte/Bit synchronous Transmission code mode type 0: NRZ • ...
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Bit 7 (NRZFM: NRZ/FM Select): Used in conjunction with the CODE1 CODE0 bits (below) to specify the transmission code type (NRZ or FM). This bit specifies MSCI decoding and encoding types. Only the NRZ type is available in asynchronous mode. ...
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CNCT1, CNCT0 = 0, 0: Specifies the full duplex communications mode (normal operation) CNCT1, CNCT0 = 0, 1: Specifies the auto-echo mode. In this mode, input data via the RXD line is directly output to the TXD line. (If specified, ...
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Async Byte sync Bit sync HDLC Read/Write — — Initial value Underrun state control • Byte synchronous mode 0: Enters idle state immediately 1: Enters idle state after CRC transmission • Bit synchronous ...
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Bits 7 6: Reserved. These bits always read 0 and must be set to 0. Bit 5 (UDRNC: Underrun State Control): Specifies the transmit operation in underrun state in byte or bit synchronous mode. Asynchronous mode Reserved. This bit always ...
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Bit 2 (SYNCLD: SYN Character Load Enable): Specifies whether or not to transfer the SYN character specified by synchronous/address register 0 (SA0) in the data field to the receive buffer in byte synchronous mode. See section 5.3.2, Byte Synchronous Mode. ...
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MSCI RX Clock Source Register (RXS) The RX clock source register (RXS) specifies the receive clock source and the baud rate of the baud rate generator (BRG) in the receiver. For the baud rate generator, see section 5.6, Baud ...
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Bit 7: Reserved. This bit always reads 0 and must be set to 0. Bits 6 4 (RXCS2 RXCS0: Receive Clock Source): Specify the receive clock source. Asynchronous/Byte synchronous/Bit synchronous mode RXCS2 RXCS0 = suppressor does not ...
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MSCI TX Clock Source Register (TXS) The TX clock source register (TXS) specifies the transmit clock source and the baud rate of the baud rate generator (BRG) in the transmitter. For details on the baud rate generator, see section ...
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Bit 7: Reserved. This bit always reads 0 and must be set to 0. Bits 6–4 (TXCS2–TXCS0: Transmit Clock Source): Specify the transmit clock source. Asynchronous/Byte synchronous/Bit synchronous mode TXCS2–TXCS0 = TXCS2–TXCS0 = ...
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MSCI Time Constant Register (TMC) The time constant register (TMC) specifies the value (1–256 loaded to the reload timer in the internal baud rate generator (BRG). For details, see section 5.6, MSCI Baud Rate Generator. This register ...
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Specific values are listed in table 5.21, Register Values and Bit Rates in Asynchronous Mode, and table 5.22, Register Values and Bit Rates in Byte Synchronous/Bit Synchronous Mode. 5.2.8 MSCI Command Register (CMD) The command register (CMD) specifies the command ...
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Table 5.1 Transmit Commands Command Name (Set Value) Function TX reset (01H) Immediately sets the transmitter to TX disable state (the transmit line goes to mark): clears the transmit buffer, transmit status in status registers 3–0 (ST3–ST0), and the BRK ...
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Table 5.1 Transmit Commands (cont) Command Name (Set Value) Function End-of-message (06H) Specifies the transmit character, which is first transferred to the transmit buffer after this command is issued, as the last character of the frame. When the transmit character ...
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Table 5.2 Receive Commands (cont) Command Name (Set Value) Function RX enable (12H) Sets the receiver to start bit search state in asynchronous mode, SYN1 wait state in byte synchronous mode, and flag wait state in bit synchronous mode. When ...
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Table 5.2 Receive Commands (cont) Command Name (Set Value) Function Forcing RX CRC Forcibly starts CRC calculation of the 8-bit data in the RX delay register. calculation (18H) In byte synchronous mode, this command must be issued after the second ...
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MSCI Status Register 0 (ST0) Status register 0 (ST0) indicates the status of interrupts (TXINT and RXINT) and the transmit/receive buffer. When any bit of this register is set MPU interrupt request is generated (if enabled). ...
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Bit 7 (TXINT: TXINT Interrupt): Indicates whether or not the TXINT interrupt has occurred. A TXINT interrupt request is issued to the MPU when this bit and the TXINTE bit of interrupt enable register 0 (IE0) are both 1. Asynchronous/Byte ...
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In other words, RXINT is set to 1 under one of the following conditions: The CLMDE bit is set to 1 and no RXD transition has been detected in the ADPLL window twice successively in FM mode. The SYNCDE/FLGDE bit ...
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TXRDY = enable state, indicates that the data byte count in the transmit buffer is equal to or less than TXF0, or indicates that the data byte count in the transmit buffer is NOT equal to or ...
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RXRDY = 1: Indicates that the data byte count in the receive buffer is equal to or greater than RXF + 1, or that at least one byte of data still remains in the receive buffer after the data byte ...
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MSCI Status Register 1 (ST1) Status register 1 (ST1) indicates status information such as break start/stop detection in asynchronous mode, underrun error, and SYN pattern detection in byte synchronous mode, underrun error, flag, abort, DPLL error, and idle start ...
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Bit 7 (UDRN: Underrun Error): Indicates whether or not an underrun error has occurred in byte or bit synchronous mode. (In asynchronous mode, underrun errors do not occur.) This bit is cleared when 1 is written to this bit position. ...
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Bit 3 (CCTS: CTS Line Level Change): Indicates whether or not the CTS line level has changed. This bit is cleared when 1 is written to this bit position. Asynchronous/Byte synchronous/Bit synchronous mode Indicates that the CTS line level has ...
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MSCI Status Register 2 (ST2) Status register 2 (ST2) indicates status information such as parity/MP bit value, parity error detection, and framing error detection in asynchronous mode, CRC error detection in byte synchronous mode, receive frame end, short frame, ...
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PMP * Async — Byte sync * EOM SHRT Bit sync HDLC Read/Write R/W R/W Initial value 0 0 Receive end of message • Bit synchronous mode 0: Receive frame end not detected 1: Receive frame end ...
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EOM = 0: Indicates that the receive frame has not ended EOM = 1: Indicates that the receive frame has ended Bit 6 (PMP/SHRT: Parity/MP Bit/Short Frame): Indicates the parity/MP bit value in asynchronous mode, or short frame detection in ...
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Reserved. This bit always reads 0 and can be set Bit synchronous mode The ABT bit indicates whether or not an abort end frame has been detected. This bit is set the character ...
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Reserved. This bit always reads 0 and can be set Byte synchronous/Bit synchronous mode The CRCE bit indicates whether or not a CRC error has occurred. When the CRCCC bit of MD0 is 1, this bit ...
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If enabled, an interrupt request is generated when the residual bit data is ready to be read. However, in bit synchronous mode, the residual bit interrupt must be disabled because receive status is usually read from the frame status ...
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MSCI Status Register 3 (ST3) Status register 3 (ST3) indicates data transmit status in bit synchronous mode, whether or not the ADPLL is in search mode in byte or bit synchronous mode, and also indicates the CTS and DCD ...
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Bits 7 6: Reserved. These bits always read 0. Bit 5 (SLOOP: Sending on Loop): Indicates MSCI data transmission status in bit synchronous mode. This bit is set to 1 when the MSCI is transmitting data, and is cleared otherwise. ...
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TXENBL = 1:Indicates that the transmitter is enabled Bit 0 (RXENBL: RX Enable): Indicates whether the receiver is enabled or disabled. Receiver enable/disable selection is performed by a command. This is a read-only bit, and writing to it has no ...
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Data read TRB Receive buffer Figure 5.5 Frame Status Register (FST) A frame end interrupt is generated when status data is set in FST. After the interrupt has been generated, the status of the received frame can be read from ...
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MSCI Interrupt Enable Register 0 (IE0) Interrupt enable register 0 (IE0) enables or disables the TXINT, RXINT, TXRDY, and RXRDY interrupt requests. Interrupt requests are issued to the MPU when both the status register 0 (ST0) bits and the ...
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Bits 5 2: Reserved. These bits always read 0 and must be set to 0. Bit 1 (TXRDYE: TXRDY Interrupt Enable): The function of this bit is described below. Asynchronous/Byte synchronous/Bit synchronous mode TXRDYE = 0: Disables an interrupt request ...
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MSCI Interrupt Enable Register 1 (IE1) Interrupt enable register 1 (IE1) enables or disables interrupt requests when the status bits of status register 1 (ST1) are set to 1. For details on interrupts, see section 5.7, Interrupts. 7 — ...
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Bit 7 (UDRNE: UDRN Interrupt Enable): The function of this bit is described below. Asynchronous mode Reserved. This bit always reads 0 and must be set to 0. Byte synchronous/Bit synchronous mode UDRNE = 0: Disables an interrupt set by ...
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Asynchronous/Byte synchronous/Bit synchronous mode CDCDE = 0: Disables an interrupt set by the CDCD bit of ST1 CDCDE = 1: Enables an interrupt set by the CDCD bit of ST1; the RXINT bit of ST0 is set to 1 when ...
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MSCI Interrupt Enable Register 2 (IE2) Interrupt enable register 2 (IE2) enables or disables interrupt requests when the status bits of status register 2 (ST2) are set to 1. For details on interrupts, see section 5.7, Interrupts ...
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Bit 7 (EOME: EOM Interrupt Enable): The function of this bit is described below. Asynchronous/Byte synchronous mode Reserved. This bit always reads 0 and must be set to 0. Bit synchronous mode EOME = 0: Disables an interrupt set by ...
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Bit 3 (OVRNE: OVRN Interrupt Enable): The function of this bit is described below. Asynchronous/Byte synchronous/Bit synchronous mode OVRNE = 0: Disables an interrupt set by the OVRN bit of ST2 OVRNE = 1: Enables an interrupt set by the ...
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MSCI Frame Interrupt Enable Register (FIE) The frame interrupt enable register (FIE) enables or disables interrupt requests when the EOMF bit of the frame status register (FST) is set — * Async Byte sync Bit sync ...
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MSCI Synchronous/Address Register 0 (SA0) Synchronous/address register 0 (SA0) specifies the SYN character pattern for reception in byte synchronous mono-sync mode, the low-order eight bits of the SYN character pattern for transmission and reception in byte synchronous bi-sync mode, ...
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Bits 7 0 (SA07 SA00: Synchronous/Address): The function of these bits is described below. Asynchronous mode Not used Byte synchronous (mono- or bi-sync) mode The SA07 SA00 bits specify bits the SYN character pattern for reception in ...
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Synchronous/Address Register 1 (SA1) Synchronous/address register 1 (SA1) specifies the SYN character pattern for transmission in byte synchronous mono-sync or byte synchronous external-sync mode, the SYN character pattern for transmission and reception in byte synchronous bi-sync mode, and the ...
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Bits 7 0 (SA17 SA10: Synchronous/Address): The function of these bits is described below. Asynchronous mode Not used Byte synchronous mode The SA17 SA10 bits specify bits the SYN character pattern for transmission in byte synchronous mono-sync ...
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MSCI Idle Pattern Register (IDL) The idle pattern register (IDL) specifies the idle pattern output by the transmitter when idle state. 7 — Async Byte sync IDL7 Bit sync HDLC Read/Write R/W Initial value 1 Note: ...
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MSCI TX/RX Buffer Register (TRB: TRBH, TRBL) The TX/RX buffer register (TRB: TRBH, TRBL), located at the top of the 32-stage transmit/receive buffer (TX/RX buffer), interfaces with the internal data bus. Although the TX and RX buffers are physically ...
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TRBH Bits 7 0 (TRB15 TRB8/TRBH7 TRBH0: TX/RX Buffer High Byte (TRBH)): The function of these bits is described below. Asynchronous/Byte synchronous/Bit synchronous mode Reading TRBH bits 7 0 reads a receive character from the receive buffer. If data is ...
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Table 5.8 TRB Read Operation in CPU Modes 2, 3 Read Mode Accessed Register* Word read TRBH TRBL Byte read TRBH TRBL Notes: 1. Data byte count in the receive buffer is reflected by the CDE1 and CDE0 bits of ...
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Table 5.9 TRB Write Operation in CPU Mode 0 Read Mode Accessed Register* Word write TRBH TRBL Byte write TRBH TRBL Table 5.10 TRB Write Operation in CPU Mode 1 Read Mode Accessed Register* Byte write TRBH TRBL Table 5.11 ...
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B A Data (a) 2 Empty Bytes Figure 5.9 Empty Data Byte Arrangement in Transmit Buffer A Data Data (b) 1 Empty Byte Rev. 0, 07/98, page 167 of 453 ...
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MSCI RX Ready Control Register (RRC) The RX ready control register (RRC) determines the MSCI RX ready (RXRDY) activation condition. The function of this register is the same in asynchronous, byte synchronous, and bit synchronous modes. 7 Async — ...
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MSCI TX Ready Control Register 0 (TRC0) TX ready control register 0 (TRC0) determines the MSCI TX ready (TXRDY) activation condition. The function of this register is the same in asynchronous, byte synchronous, and bit synchronous modes. 7 Async ...
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MSCI TX Ready Control Register 1 (TRC1) TX ready control register 1 (TRC1) determines the MSCI TX ready (TXRDY) inactivation condition. The function of this register is the same in asynchronous, byte synchronous, and bit synchronous modes. 7 Async ...
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MSCI Current Status Register 0 (CST0) Current status register 0 (CST0) monitors the top stage of the MSCI's 32-stage status FIFO. This register indicates whether or not data is in the top stage of the receive buffer, and if ...
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CDE0 = 1: Indicates that data is in the top stage of the receive buffer This register monitors the status of only the top stage of the receive status FIFO in CPU modes 0, 2, and 3, which is different ...
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Bits 7 2: Indicate the status of the data in the second stage of the receive buffer. These bits are arranged in the same way as bits status register 2 (ST2). When data is in the second ...
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Operation 5.3.1 Asynchronous Mode In asynchronous mode, a start bit and stop bit(s) are appended to the character before transmission to synchronize character. In this mode, the transmission line is normally high (mark); when the line goes low, that ...
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The transmit and receive bit rates can be independently selected from the input frequency ratios 1/1, 1/16, 1/32, or 1/64 by using the BRATE1 BRATE0 bits of MD1 (figure 5.11). (The selected bit rate is used for both transmission and ...
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Transmission Operation: Figure 5.13 is the state transition diagram for transmission in asynchronous mode. TX disable state The transmitter is placed in TX disable state by a hardware reset, a channel reset reset disable command. ...
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Initialization by reset "TX disable" not issued and data remaining in transmit buffer TX disable "TX enable" issued state "TX disable" issued "TX reset" or "channel reset" issued in any state Start bit transmit state ...
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Transmit character writing Start bit transmission Idle state D Transmit 0 data Transmit clock Start bit Transmit data Transmit clock 16, 32 clock cycles (b) 1/16, 1/32 or 1/64 Clock Mode Figure 5.14 Transmission Operation Rev. 0, 07/98, ...
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Reception Operation: Figure 5.15 is the state transition diagram for reception in asynchronous mode. RX disable state The receiver is placed in RX disable state by a hardware reset, a channel reset reset disable command. ...
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Initialization by reset "RX enable" issued RX disable state Space detected "RX reset", "RX disable" or "channel reset" issued in any stale Start bit check state No mark Break end detected wait state Note: Command names are enclosed in double ...
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The timing of sampling receive data is shown in figures 5.16 (a) and (b). This example uses an 8-bit character and one stop bit, with parity. Receive data D 0 Sampling Start bit search Start bit detected D Receive data ...
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Reception operation starts when an RX enable command is issued. In 1/1 clock mode, the receiver searches for a start bit at the rising edge of each clock pulse. On detecting a space (low level), the receiver begins character assembly ...
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Receive data Sampling timing Start bit search Space detected (a) True Start Bit Detection Receive data Sampling timing Start bit search Space detected (b) False Start Bit (Noise) Detection Figure 5.18 Start Bit Sampling Character assembly Start bit check (space ...
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In the character assembly process, the receiver samples data every other bit cycle. On detecting the most significant bit (MSB) or the parity bit (if present), the receiver checks the stop bit after a delay of one bit cycle. If ...