MC100EP446FA ON Semiconductor, MC100EP446FA Datasheet

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MC100EP446FA

Manufacturer Part Number
MC100EP446FA
Description
IC CONV 8BIT SER/PAR ECL 32LQFP
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100EP446FA

Interface
Differential
Voltage - Supply
3 V ~ 5.5 V
Package / Case
32-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Applications
-
Other names
MC100EP446FAOS

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MC100EP446FA
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MC10EP446, MC100EP446
3.3 V/5 V 8‐Bit
CMOS/ECL/TTL Data Input
Parallel/Serial Converter
Description
converter. The device is designed with unique circuit topology to
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence
from parallel data into a serial data stream is from bit D0 to D7. The
parallel input pins D0−D7 are configurable to be threshold controlled by
CMOS, ECL, or TTL level signals. The serial data rate output can be
selected at internal clock data rate or twice the internal clock data rate
using the CKSEL pin.
circuitry (CKEN). In either CKSEL modes, the internal flip−flops are
triggered on the rising edge for CLK and the multiplexers are switched
on the falling edge of CLK, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Additionally, V
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 10
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC10/100EP446 is an integrated 8−bit parallel to serial data
Control pins are provided to reset (SYNC) and disable internal clock
The 100 Series devices contain temperature compensation network.
3.2 Gb/s Typical Data Rate Capability
Differential Clock and Serial Outputs
V
Asynchronous Data Reset (SYNC)
PECL Mode Operating Range:
NECL Mode Operating Range:
Open Input Default State
Safety Clamp on Inputs
Parallel Interface Can Support PECL, TTL or CMOS
Pb−Free Packages are Available*
BB
Output for Single-ended Input Applications
V
V
CC
CC
BB
= 3.0 V to 5.5 V with V
= 0 V with V
pin is provided for single−ended input condition.
EE
= −3.0 V to −5.5 V
EE
= 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional marking information, refer to
CASE 488AM
xxx
A
WL, L
YY, Y
WW, W = Work Week
G or G
(Note: Microdot may be in either location)
Application Note AND8002/D.
CASE 873A
MN SUFFIX
FA SUFFIX
LQFP−32
QFN32
1
ORDERING INFORMATION
32
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
http://onsemi.com
MARKING DIAGRAMS*
Publication Order Number:
1
AWLYYWWG
AWLYYWWG
MCxxx
EP446
MCxxx
EP446
G
MC10EP446/D

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MC100EP446FA Summary of contents

Page 1

... Parallel Interface Can Support PECL, TTL or CMOS • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 April, 2009 − Rev. 10 ...

Page 2

MC10EP446 MC100EP446 SYNC 29 SYNC BB2 Warning: All V and V pins ...

Page 3

Table 2. TRUTH TABLE HIGH Pin CKSEL S : PCLK = 8:1 OUT CLK 1:1 OUT CLK S OUT CKEN Synchronously Disables Normal Parallel to Serial Conversion SYNC Asynchronously Resets Internal Flip−Flops* *The rising edge of SYNC will ...

Page 4

...

Page 5

Table 5. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 6

Table 7. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

Table 8. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 8

Table 9. 10EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 9

Table 11. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 15 Output LOW Voltage (Note 15 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 10

Table 13. AC CHARACTERISTICS Symbol Characteristic f Maximum Frequency max (Figure 15) CKSEL High CKSEL Low t , Propagation Delay to Output Differential PLH t CKSEL = 0 CLK TO S PHL CLK TO PCLK CKSEL = 1 CLK TO ...

Page 11

CLK Data Setup Time Figure 4. Setup and Hold Time for Data SYNC SYNC t s CLK CLK Figure 5. Setup Time for SYNC Data Valid − CLK CKEN Figure 6. Setup and Hold ...

Page 12

The MC10/100EP446 is an integrated 8:1 parallel to serial converter. An attribute for EP446 is that the parallel inputs D0–D7 (Pins 17 – 24) can be configured to accept either CMOS, ECL, or TTL level signals by a combination of ...

Page 13

Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched ¬ to when the data is seen on the th ­ the rising edge of the 14 S OUT on the rising edge of ...

Page 14

The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt ...

Page 15

For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling edge of SYNC ¬, followed by the falling edge CLK ­, on the second rising edge of ...

Page 16

The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the falling ...

Page 17

CKSEL Low 600 500 400 300 200 100 0 0 500 1000 INPUT CLOCK FREQUENCY (MHz) Figure 15. Typical V OUTPP Figure 16. SOUT System Jitter Measurement (Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on ...

Page 18

... ORDERING INFORMATION Device MC10EP446FA MC10EP446FAG MC10EP446FAR2 MC10EP446FAR2G MC100EP446FA MC100EP446FAG MC100EP446FAR2 MC100EP446FAR2G MC10EP446MNG MC100EP446MNG MC10EP446MNR4G MC100EP446MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D ...

Page 19

−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...

Page 20

... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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