74HC4053D,652 NXP Semiconductors, 74HC4053D,652 Datasheet

IC MUX/DEMUX TRIPLE 2X1 16SOIC

74HC4053D,652

Manufacturer Part Number
74HC4053D,652
Description
IC MUX/DEMUX TRIPLE 2X1 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC4053D,652

Package / Case
16-SOIC (0.154", 3.90mm Width)
Function
Multiplexer/Demultiplexer
Circuit
3 x 2:1
On-state Resistance
60 Ohm
Voltage Supply Source
Dual Supply
Voltage - Supply, Single/dual (±)
±2 V ~ 10 V
Current - Supply
16µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Propagation Delay Time
60 ns
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Switches
Triple
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3963-5
74HC4053D
74HC4053D
933714840652
1. General description
2. Features and benefits
3. Applications
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state)
by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent
of S1 to S3.
V
The V
74HCT4053. The analog inputs/outputs (Y0 to Y7, and nZ) can swing between V
positive limit and V
For operation as a digital multiplexer/demultiplexer, V
ground).
CC
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 5 — 18 January 2011
Wide analog input voltage range from −5 V to +5 V
Low ON resistance:
Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
CC
80 Ω (typical) at V
70 Ω (typical) at V
60 Ω (typical) at V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
EE
as a negative limit. V
CC
CC
CC
− V
− V
− V
EE
EE
EE
= 4.5 V
= 6.0 V
= 9.0 V
CC
− V
EE
may not exceed 10.0 V.
EE
is connected to GND (typically
Product data sheet
CC
as a

Related parts for 74HC4053D,652

74HC4053D,652 Summary of contents

Page 1

Triple 2-channel analog multiplexer/demultiplexer Rev. 5 — 18 January 2011 1. General description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B specified in compliance with JEDEC standard no. ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74HC4053N 74HCT4053N −40 °C to +125 °C 74HC4053D 74HCT4053D −40 °C to +125 °C 74HC4053DB 74HCT4053DB −40 °C to +125 °C 74HC4053PW 74HCT4053PW −40 °C to +125 °C ...

Page 3

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram Fig 2. Logic symbol 74HC_HCT4053 Product data sheet Triple 2-channel analog multiplexer/demultiplexer LOGIC S1 11 LEVEL DECODER CONVERSION LOGIC S2 10 LEVEL CONVERSION LOGIC S3 9 LEVEL CONVERSION 8 7 GND V EE 1Y0 12 1Y1 2Y0 2 2Y1 3Y0 5 3 3Y1 ...

Page 4

... NXP Semiconductors from logic Fig 4. Schematic diagram (one switch) 6. Pinning information 6.1 Pinning 74HC4053 74HCT4053 1 2Y1 2Y0 2 3Y1 3Y0 GND 8 Fig 5. Pin configuration DIP16, SO16, and (T)SSOP16 74HC_HCT4053 Product data sheet Triple 2-channel analog multiplexer/demultiplexer 1Y1 12 1Y0 001aae127 Fig 6. All information provided in this document is subject to legal disclaimers. ...

Page 5

... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin GND 8 S1, S2, S3 11, 10, 9 1Y0, 2Y0, 3Y0 12 1Y1, 2Y1, 3Y1 13 1Z, 2Z, 3Z 14, 15 Functional description [1] Table 3. Function table Inputs [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. ...

Page 6

... NXP Semiconductors For SO16 packages: above 70 °C the value of P [3] For SSOP16 and TSSOP16 packages: above 60 °C the value of P For DHVQFN16 packages: above 60 °C the value Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage ...

Page 7

... NXP Semiconductors 10. Static characteristics Table 6. R resistance per switch for 74HC4053 and 74HCT4053 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os − For 74HC4052: V ...

Page 8

... NXP Semiconductors Table 6. R resistance per switch for 74HC4053 and 74HCT4053 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os − For 74HC4052: V GND or V ...

Page 9

... NXP Semiconductors from select Sn input nYn GND V is − -------- - Fig 9. Test circuit for measuring R Table 7. Static characteristics for 74HC4053 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. ...

Page 10

... NXP Semiconductors Table 7. Static characteristics for 74HC4053 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter I supply current CC C input capacitance I C switch capacitance sw = − ...

Page 11

... NXP Semiconductors Table 7. Static characteristics for 74HC4053 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter I input leakage current I I OFF-state leakage ...

Page 12

... NXP Semiconductors Table 8. Static characteristics for 74HCT4053 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input ...

Page 13

... NXP Semiconductors and and Fig 11. Test circuit for measuring OFF-state current and V = open-circuit and V = open-circuit Fig 12. Test circuit for measuring ON-state current 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input. ...

Page 14

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-on time turn-off time ...

Page 15

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-on time turn-off time ...

Page 16

... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-off time off ...

Page 17

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-off time off ...

Page 18

... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4053 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-off time off ...

Page 19

... NXP Semiconductors E, Sn inputs 0.5 × V For 74HC4053 For 74HCT4053 1 Fig 14. Turn-on and turn-off times Definitions for test circuit; see R = termination resistance should be equal to the output impedance load capacitance including jig and probe capacitance load resistance Test selection switch. Fig 15. Test circuit for measuring AC performance ...

Page 20

... NXP Semiconductors Table 11. Test data Test Input PHL PLH [ PZH PHZ [ PZL PLZ [ ns; when measuring max [2] V values For 74HC4053 For 74HCT4053 11.1 Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = the input voltage at pins nYn or nZ, whichever is assigned as an input. ...

Page 21

... NXP Semiconductors Fig 16. Test circuit for measuring sine-wave distortion V = 4.5 V; GND = Test circuit 0 iso (dB 100 10 b. Isolation (OFF-state function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) 74HC_HCT4053 Product data sheet Triple 2-channel analog multiplexer/demultiplexer nYn/nZ nZ/nYn GND 0.1 F nYn/nZ nZ/nYn ...

Page 22

... NXP Semiconductors Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers G Fig 19. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4053 Product data sheet Triple 2-channel analog multiplexer/demultiplexer 0 nYn/nZ nZ/nYn GND nYn/nZ nZ/nYn V GND Sn, E nYn nZ V GND ...

Page 23

... NXP Semiconductors V = 4.5 V; GND = Test circuit (dB Typical frequency response Fig 20. Test circuit for frequency response 74HC_HCT4053 Product data sheet Triple 2-channel analog multiplexer/demultiplexer nYn/nZ nZ/nYn GND EE = −4 Ω kΩ All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 January 2011 74HC4053 ...

Page 24

... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 25

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 26

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 23. Package outline SOT338-1 (SSOP16) ...

Page 27

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 28

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 29

... Release date 74HC_HCT4053 v.5 20110118 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Figure 6 corrected (errata) 74HC_HCT4053 v.4 20060509 74HC_HCT4053 v ...

Page 30

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 31

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT4053 Product data sheet 74HC4053 ...

Page 32

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 13 11.1 Additional dynamic characteristics . . . . . . . . . 20 12 Package outline ...

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