HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet
HSDC-JAKIT1W2/DB
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HSDC-JAKIT1W2/DB Summary of contents
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ADC1413D series Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 5 — 9 February 2011 1. General description The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance ...
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... NXP Semiconductors 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment 4. Ordering information Table 1. Ordering information Type number Sampling frequency (Msps) ADC1413D125HN/C1 125 ADC1413D105HN/C1 105 ADC1413D080HN/C1 80 ADC1413D065HN/C1 65 ADC1413D_SER Product data sheet Dual 14-bit ADC; serial JESD204A interface ...
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... NXP Semiconductors 5. Block diagram INAP T/H INPUT STAGE INAM CLKP DLL PLL CLKM INBP T/H INPUT STAGE INBM ADC1413D Fig 1. Block diagram ADC1413D_SER Product data sheet Dual 14-bit ADC; serial JESD204A interface CFG ( SDIO SCLK CS ERROR SPI CORRECTION AND DIGITAL PROCESSING ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB INBM ADC1413D_SER Product data sheet 1 INAP INAM 2 VCMA 3 REFAT 4 5 REFAB 6 AGND CLKP 7 CLKM 8 AGND 9 10 REFBB ...
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... NXP Semiconductors Table 2. Symbol INBP VDDA VDDA SCLK SDIO CS AGND RESET SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 DNC VDDA AGND ...
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... NXP Semiconductors Table 2. Symbol VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. [2] OTRA stands for “OuT of Range A”. OTRB stands for “OuT of Range B” 7. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V digital supply voltage DDD I analog supply current DDA I digital supply current DDD P total power dissipation tot P power dissipation Clock inputs: pins CLKP and CLKM (AC-coupled) Low-Voltage Positive Emitter-Coupled Logic (LVPECL) ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter B input bandwidth i V differential input voltage I(dif) Voltage controlled regulator output: pins VCMA and VCMB V common-mode output O(cm) voltage I common-mode output O(cm) current Reference voltage input/output: pin VREF V voltage on pin VREF VREF Data outputs: pins CMLPA, CMLNA Output levels 1.8 V ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter DNL differential non-linearity E offset error offset E gain error G M channel-to-channel gain G(CTC) matching Supply PSRR power supply rejection ratio [1] Typical values measured at V DDA = 40 C to +85 range T amb 100 differential applied to serial outputs; unless otherwise specified. ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 6. Dynamic characteristics Symbol Parameter Conditions Analog signal processing second harmonic level MHz MHz MHz 170 ...
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Table 6. Dynamic characteristics …continued Symbol Parameter Conditions IMD intermodulation distortion MHz MHz MHz 170 MHz i channel crosstalk MHz ct(ch) ...
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... NXP Semiconductors 10.3 Serial output timing The eye diagram of the serial output is shown in are: • 3.125 Gbps data rate • T amb • DC coupling with two different receiver common-mode voltages Fig 3. Fig 4. ADC1413D_SER Product data sheet = 25 °C Eye diagram receiver common-mode Eye diagram receiver common-mode All information provided in this document is subject to legal disclaimers. Rev. 5 — ...
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... NXP Semiconductors 10.4 SPI timing Table 8. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V across the full temperature range T INBP) V unless otherwise specified. Fig 5. ADC1413D_SER Product data sheet [1] SPI timing characteristics Parameter Conditions SCLK pulse width SCLK HIGH pulse ...
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... NXP Semiconductors 11. Application information 11.1 Analog inputs 11.1.1 Input stage description The analog input of the ADC1413D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... NXP Semiconductors 11.1.2 Anti-kickback circuitry Anti-kickback circuitry (RC filter in charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ...
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... NXP Semiconductors Fig 9. The configuration shown in both cases, the choice of transformer is a compromise between cost and performance. 11.2 System reference and power management 11.2.1 Internal/external reference The ADC1413D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (see control bits INTREF[2:0] (when bit INTREF_EN = logic 1 ...
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... NXP Semiconductors VREF SENSE Fig 10. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 10. Mode Internal Internal External Internal, SPI mode (Figure Figure 11 required reference voltage source. ADC1413D_SER Product data sheet REFERENCE AMP EXT_ref ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 11. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 13. External reference (p- (p-p) full-scale 11.2.2 Programmable full-scale The full-scale is programmable between 1 V (p- (p-p) (see Table 11. INTREF[2:0] 000 001 010 011 100 101 ...
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... NXP Semiconductors 11.2.3 Common-mode output voltage (V An 0.1 F filter capacitor should be connected between pins VCMA and VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point ...
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... NXP Semiconductors a. Sine clock input c. LVPECL clock input Fig 17. Differential clock input 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via 5 k internal resistors. Fig 18. Equivalent input circuit ADC1413D_SER Product data sheet ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI (see single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 11.3.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the input clock signal duty cycle ...
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... NXP Semiconductors Fig 20. CML output connection to the receiver (AC-coupled) 11.5 JESD204A serializer For more information about the JESD204A standard refer to the JEDEC web site. 11.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side ...
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... NXP Semiconductors ADC_MODE[1:0] PRBS 11 DUMMY AND CS ADC_PD ADC A × 1 frame CLK PLL × F AND character CLK ASSEMBLY DLL × 10F bit CLK ADC ADC_PD AND DUMMY CS 11 PRBS ADC_MODE[1:0] Fig 22. Detailed view of the JESD204A serializer with debug functionality 11.5.2 ADC core output codes versus input voltage Table 13 Table 13 ...
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... NXP Semiconductors Table 13. INP INM (V) Offset binary +0.9996338 +0.9997559 +0.9998779 +1 > +1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1413D serial interface is a synchronous serial communications port allowing easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. ...
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... NXP Semiconductors The steps for a data transfer: 1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits ...
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Table 17. Register allocation map [1] Address Register name Access (hex) Bit 7 ADC control register 0003 Channel index R/W - 0005 Reset and R/W SW_RST Power-down modes 0006 Clock R/W - 0008 Vref R/W - 0013 Offset R/W - ...
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Table 17. Register allocation map …continued [1] Address Register name Access (hex) Bit 7 0826 Cfg_7_CS_N R/W* 0 0827 Cfg_8_Np R/W 0 0828 Cfg_9_S R/W* 0 0829 Cfg_10_HD_CF R/W* HD 082C Cfg_01_2_LID R/W* 0 082D Cfg_02_2_LID R/W* 0 084C Cfg01_13_FCHK ...
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... NXP Semiconductors 11.6.3 Register description 11.6.3.1 ADC control registers Table 18. Register Channel index (address 0003h) Default values are highlighted. Bit Symbol Access ADCB R/W 0 ADCA R/W Table 19. Register Reset and Power-down mode (address 0005h) Default values are highlighted. Bit Symbol Access ...
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... NXP Semiconductors Table 21. Register Vref (address 0008h) Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Digital Offset adjustment (address 0013h) Default values are highlighted. Register Offset Decimal +31 ... 0 ... 32 Table 23. Register Test pattern 1 (address 0014h) Default values are highlighted. ...
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... NXP Semiconductors Table 24. Register Test pattern 2 (address 0015h) Default values are highlighted. Bit Symbol Access TESTPAT_2[13:6] R/W Table 25. Register Test pattern 3 (address 0016h) Default values are highlighted. Bit Symbol Access TESTPAT_3[5:0] R 11.6.4 JESD204A digital control registers Table 26. Ser_Status (address 0801h) Default values are highlighted. ...
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... NXP Semiconductors Table 28. Ser_Cfg_Setup (address 0803h) Default values are highlighted. Bit Symbol CFG_SETUP[3:0] Table 29. JESD204A configuration table CFG_SETUP[3:0] ADC A ADC B 0 0000 0001 0010 0011 ON OFF 4 0100 OFF ON 5 0101 ON OFF 6 0110 ON OFF 7 0111 OFF ON 8 1000 OFF ON 9 1001 10 1010 ...
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... NXP Semiconductors Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit Symbol TRISTATE_CFG_PINS 5 SYNC_POL 4 SYNC_SINGLE_ENDED R REV_SCR 1 REV_ENCODER 0 REV_SERIAL Table 31. Ser_Control2 (address 0806h) Default values are highlighted. Bit Symbol SWAP_LANE_0_1 0 SWAP_ADC_A_B Table 32. Ser_Analog_Ctrl (address 0808h) Default values are highlighted. Bit Symbol SWING_SEL[2:0] ...
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... NXP Semiconductors Table 33. Ser_ScramblerA (address 0809h) Default values are highlighted. Bit Symbol LSB_INIT[6:0] Table 34. Ser_ScramblerB (address 080Ah) Default values are highlighted. Bit Symbol MSB_INIT[7:0] Table 35. Ser_PRBS_Ctrl (address 080Bh) Default values are highlighted. Bit Symbol PRBS_TYPE[1:0] Table 36. Cfg_0_DID (address 0820h) Default values are highlighted. ...
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... NXP Semiconductors Table 40. Cfg_5_K (address 0824h) Default values are highlighted. Bit Symbol K[4:0] Table 41. Cfg_6_M (address 0825h) Default values are highlighted. Bit Symbol Table 42. Cfg_7_CS_N (address 0826h) Default values are highlighted. Bit Symbol CS[ N[3:0] Table 43. Cfg_8_Np (address 0827h) Default values are highlighted. ...
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... NXP Semiconductors Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol LID[4:0] Table 48. Cfg01_13_FCHK (address 084Ch) Default values are highlighted. Bit Symbol FCHK[7:0] Table 49. Cfg02_13_FCHK (address 084Dh) Default values are highlighted. Bit Symbol FCHK[7:0] Table 50. Lane0_0_Ctrl (address 0870h) Default values are highlighted. ...
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... NXP Semiconductors Table 50. Lane0_0_Ctrl (address 0870h) Default values are highlighted. Bit Symbol 0 LANE_PD Table 51. Lane1_0_Ctrl (address 0871h) Default values are highlighted. Bit Symbol SCR_IN_MODE LANE_MODE[1: LANE_POL 1 LANE_CLK_POS_EDGE R/W 0 LANE_PD ADC1413D_SER Product data sheet …continued Access Value Description R/W lane power-down control: ...
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... NXP Semiconductors Table 52. ADCA_0_Ctrl (address 0890h) Default values are highlighted. Bit Symbol ADC_MODE[1: ADC_PD Table 53. ADCB_0_Ctrl (address 0891h) Default values are highlighted. Bit Symbol ADC_MODE[1: ADC_PD ADC1413D_SER Product data sheet Access Value Description - 00 not used R/W defines input type of JESD204A unit: ...
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... NXP Semiconductors 12. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index area Dimensions (1) Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 54. Acronym ADC DCS ESD IF IMD LSB LVCMOS LVPECL MSB OTR PRBS SFDR SNR SPI TX ADC1413D_SER Product data sheet Abbreviations Description Analog-to-Digital Converter Duty Cycle Stabilizer ElectroStatic Discharge Intermediate Frequency InterModulation Distortion Least Significant Bit Low Voltage Complementary Metal Oxide Semiconductor ...
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... NXP Semiconductors 14. Revision history Table 55. Revision history Document ID ADC1413D_SER v.5 Modifications: ADC1413D_SER v.4 ADC1413D_SER v.3 ADC1413D065_080_105_125_2 20090604 ADC1413D065_080_105_125_1 20090528 ADC1413D_SER Product data sheet Release date Data sheet status 20110209 Product data sheet • Data sheet status changed from Preliminary to Product. • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 Clock and digital output timing . . . . . . . . . . . . 11 10 ...