74LVC2G53DP,125 NXP Semiconductors, 74LVC2G53DP,125 Datasheet - Page 12

IC MUX/DEMUX 2X1 8TSSOP

74LVC2G53DP,125

Manufacturer Part Number
74LVC2G53DP,125
Description
IC MUX/DEMUX 2X1 8TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
Analog Multiplexerr
Datasheet

Specifications of 74LVC2G53DP,125

Package / Case
8-TSSOP
Function
Multiplexer/Demultiplexer
Circuit
1 x 2:1
On-state Resistance
6 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
1.65 V ~ 5.5 V
Current - Supply
0.1µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Channels
1 Channel
On Resistance (max)
34 Ohm (Typ) @ 1.95 V
On Time (max)
6.7 ns (Typ) @ 1.95 V
Off Time (max)
6.8 ns (Typ) @ 1.95 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Power Dissipation
250 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Switches
Single
Switch Current (typ)
0.0001 mA @ 5.5 V
Package
8TSSOP
Maximum On Resistance
195@1.95V Ohm
Maximum Propagation Delay Bus To Bus
2.5@1.95V@-40C to 125C|1.5@2.7V@-40C to 125C|1@3.6V@-40C to 125C|0.8@5.5V@-40C to 125C ns
Maximum Low Level Output Current
50 mA
Multiplexer Architecture
2:1
Maximum Turn-off Time
6.8(Typ)@1.95V ns
Maximum Turn-on Time
6.7(Typ)@1.95V ns
Power Supply Type
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC2G53DP-G
74LVC2G53DP-G
935280383125
NXP Semiconductors
Table 10.
74LVC2G53
Product data sheet
Supply voltage
V
1.65 V to 2.7 V
2.7 V to 5.5 V
Fig 16. Input (Yn or Z) to output (Z or Yn) propagation delays
Fig 17. Enable and disable times
CC
Measurement points are given in
Logic levels: V
Measurement points are given in
Logic levels: V
Measurement points
11.1 Waveforms and test circuits
OL
OL
Z, Yn
Z, Yn
and V
and V
Input
V
0.5V
0.5V
OH
OH
M
S, E input
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
CC
CC
Yn or Z
Z or Yn
output
input
Table
Table
All information provided in this document is subject to legal disclaimers.
GND
GND
V
V
V
GND
V
OH
V
CC
10.
OL
10.
V
OH
OL
V
I
I
Rev. 6 — 27 September 2010
Output
V
0.5V
0.5V
M
V
M
CC
CC
V
enabled
switch
M
V
t
PLH
M
t
PLZ
t
PHZ
V
X
V
2-channel analog multiplexer/demultiplexer
Y
V
disabled
M
switch
V
V
V
001aac361
X
OL
OL
V
M
t
PHL
+ 0.15 V
+ 0.3 V
t
PZL
t
PZH
V
M
V
M
001aad393
enabled
switch
74LVC2G53
V
V
V
Y
OH
OH
© NXP B.V. 2010. All rights reserved.
− 0.15 V
− 0.3 V
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