HEF4051BTS,118 NXP Semiconductors, HEF4051BTS,118 Datasheet
HEF4051BTS,118
Specifications of HEF4051BTS,118
HEF4051BTSDB-T
HEF4051BTSDB-T
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HEF4051BTS,118 Summary of contents
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HEF4051B 8-channel analog multiplexer/demultiplexer Rev. 09 — 25 March 2010 1. General description The HEF4051B is an 8-channel analog multiplexer/demultiplexer with three address inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information − ° All types operate from +125 Type number Package Name HEF4051BP DIP16 HEF4051BT SO16 HEF4051BTS SSOP16 HEF4051BTT TSSOP16 5. Functional diagram Fig 1. Functional diagram HEF4051B_9 Product data sheet ° C. Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package ...
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... NXP Semiconductors Fig 2. Schematic diagram (one switch 001aac278 Fig 3. Logic symbol HEF4051B_9 Product data sheet Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 09 — 25 March 2010 HEF4051B 8-channel analog multiplexer/demultiplexer 001aac281 MUX/DMUX 001aac279 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors LEVEL S1 CONVERTER LEVEL S2 CONVERTER LEVEL S3 CONVERTER LEVEL E CONVERTER Fig 5. Logic diagram HEF4051B_9 Product data sheet 8-channel analog multiplexer/demultiplexer All information provided in this document is subject to legal disclaimers. Rev. 09 — 25 March 2010 HEF4051B 001aac280 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning HEF4051B 001aak508 Fig 6. Pin configuration SOT38-4 and SOT109-1 6.2 Pin description Table 2. Pin description Symbol S1, S2, S3 Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12 HEF4051B_9 Product data sheet Fig 7. Pin Description 6 enable input (active LOW) 7 supply voltage ...
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... NXP Semiconductors 7. Functional description 7.1 Function table [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol Parameter V supply voltage ...
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... NXP Semiconductors derates linearly with 8 mW/K above 70 °C. For SO16 package: P tot For SSOP16 and TSSOP16 packages Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb Δt/ΔV input transition rise and fall rate Fig 8 ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Conditions I OFF-state Z port; S(OFF) leakage all channels OFF; current see Figure 9 Y port; per channel; see Figure 10 I supply current input Sn, E inputs I capacitance 10.1 Test circuits Fig 9. Test circuit for measuring OFF-state leakage current Z port Fig 10 ...
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... NXP Semiconductors 10.2 ON resistance Table 7. ON resistance ° μ 200 amb SW SS Symbol Parameter R ON resistance (peak) ON(peak resistance (rail) ON(rail) ΔR ON resistance mismatch ON between channels 10.2.1 ON resistance waveform and test circuit Fig 11. Test circuit for measuring R HEF4051B_9 Product data sheet = 0 V ...
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... NXP Semiconductors Fig 12. Typical function of input voltage ON 11. Dynamic characteristics Table 8. Dynamic characteristics ° for test circuit see amb SS EE Symbol Parameter t HIGH to LOW propagation delay Yn Yn; see PHL t LOW to HIGH propagation delay Yn Yn; see PLH t HIGH to OFF-state PHZ propagation delay ...
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... NXP Semiconductors Table 8. Dynamic characteristics ° for test circuit see amb SS EE Symbol Parameter t OFF-state to LOW PZL propagation delay 11.1 Waveforms and test circuit input PLH output V EE Measurement points are given in Fig 13. Yn propagation delays E input output LOW-to-OFF OFF-to-LOW output ...
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... NXP Semiconductors Test data is given in Table Definitions: DUT = Device Under Test Termination resistance should be equal to output impedance Load capacitance including test jig and probe Load resistance. L Fig 16. Test circuit for measuring switching times Table 10. Test data Input Yn and ≤ [1] For propagation delays use V ...
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... NXP Semiconductors 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics ° amb Symbol Parameter THD total harmonic distortion −3 dB frequency response f (−3dB) α isolation (OFF-state) iso V crosstalk voltage ct Xtalk crosstalk [ biased Table 12. Dynamic power dissipation P P can be calculated from the formulas shown; V ...
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... NXP Semiconductors Fig 19. Test circuit for measuring isolation (OFF-state) a. Test circuit b. Input and output pulse definitions Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch HEF4051B_9 Product data sheet 0. switch logic off on input (Sn All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Switch closed condition Fig 21. Test circuit for measuring crosstalk between switches HEF4051B_9 Product data sheet = 001aak520 All information provided in this document is subject to legal disclaimers. Rev. 09 — 25 March 2010 HEF4051B 8-channel analog multiplexer/demultiplexer Switch open condition = 001aak521 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 24. Package outline SOT338-1 (SSOP16) ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 13. Revision history Document ID Release date HEF4051B_9 20100325 HEF4051B_8 20100301 • Modifications: Table 6 “Static HEF4051B_7 20091127 HEF4051B_6 20090924 HEF4051B_5 20090826 HEF4051B_4 20050112 HEF4051B_CNV_3 19950101 HEF4051B_CNV_2 19950101 HEF4051B_9 Product data sheet 8-channel analog multiplexer/demultiplexer Data sheet status Product data sheet Product data sheet characteristics” ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 15. Contact information For more information, please visit: For sales office addresses, please send an email to: HEF4051B_9 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 09 — 25 March 2010 HEF4051B 8-channel analog multiplexer/demultiplexer © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Limiting values Recommended operating conditions Static characteristics 10.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 ...