CY7C25702KV18-550BZXI Cypress Semiconductor Corp, CY7C25702KV18-550BZXI Datasheet

CY7C25702KV18-550BZXI

Manufacturer Part Number

CY7C25702KV18-550BZXI

Description

IC SRAM DDR-II+ CIO-ODT 165FBGA

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C25702KV18-550BZXI.pdf (29 pages)

Specifications of CY7C25702KV18-550BZXI

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

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72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

■

Table 1. Selection Guide

Note

Cypress Semiconductor Corporation

Document Number: 001-66483 Rev. **

Maximum Operating Frequency

Maximum Operating Current

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

550 MHz clock for high bandwidth

2-word burst for reducing address bus frequency

Double data rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

Available in 2.5 clock cycle latency

Two input clocks (K and K) for precise DDR timing

❐

Echo Clocks (CQ and CQ) simplify data capture in high speed

systems

Data valid pin (QVLD) to indicate valid data on the output

On-die termination (ODT) feature

❐

Synchronous internally self-timed writes

DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

Operates similar to DDR I Device with 1 cycle read latency

when DOFF is asserted LOW

Core V

❐

HSTL inputs and variable drive HSTL output buffers

Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Phase-locked loop (PLL) for accurate data placement

SRAM uses rising edges only

Supported for D

Supports both 1.5V and 1.8V I/O supply

= 1.8V ± 0.1V; I/O V

[x:0]

Description

, BWS

[x:0]

DDQ

, and K/K inputs

= 1.4V to V

•

72-Mbit DDR II+ SRAM 2-Word Burst Architecture

198 Champion Court

[1]

x18

x36

550 MHz

550

740

760

970

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C25662KV18 – 8M x 8

CY7C25772KV18 – 8M x 9

CY7C25682KV18 – 4M x 18

CY7C25702KV18 – 2M x 36

Functional Description

The CY7C25662KV18, CY7C25772KV18, CY7C25682KV18,

and CY7C25702KV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C25662KV18), 9-bit words (CY7C25772KV18),

18-bit

(CY7C25702KV18) that burst sequentially into or out of the

device.

These devices have an On-Die Termination feature supported

for D

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

(2.5 Cycle Read Latency) with ODT

CY7C25662KV18, CY7C25772KV18

CY7C25682KV18, CY7C25702KV18

[x:0]

•

DDQ

500 MHz

, BWS

words

= 1.4V to V

500

690

700

890

San Jose

[x:0]

(CY7C25682KV18),

, and K/K inputs, which helps eliminate

CA 95134-1709

450 MHz

450

630

650

820

Revised March 15, 2011

400 MHz

400

580

590

750

•

36-bit

408-943-2600

MHz

Unit

words

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