ISL54220IRUZ-T Intersil, ISL54220IRUZ-T Datasheet
ISL54220IRUZ-T
Specifications of ISL54220IRUZ-T
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ISL54220IRUZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners 2.7V to 5.5V ...
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Pin Configurations ISL54220 (10 LD 3.0X3.0 TDFN) TOP VIEW PD LOGIC SEL 1 CONTROL HSD1+ 2 HSD2 GND NOTE: 1. Switches Shown for SEL = Logic “1” and OE = Logic “0”. Truth Table OE SEL ...
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... Ordering Information PART NUMBER PART (Note 5) MARKING ISL54220IRUZ-T (Notes ISL54220IRTZ (Note 3) 4220 ISL54220IRTZ-T (Notes 2, 3) 4220 ISL54220IUZ (Note 3) 54220 ISL54220IUZ-T (Notes 2, 3) 54220 ISL54220IRUEVAL1Z Evaluation Board NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Ld MSOP (Note 7, 10 Maximum Junction Temperature (Plastic Package). . Maximum Storage Temperature Range -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C V Supply Voltage Range . . . . . . . . . . . . . . . 2.7V to 5.5V DD Logic Control Input Voltage . . . . . . . . . . . . . . . . Analog Signal Range ...
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Electrical Specifications - 2.7V to 5.5V Supply PARAMETER ON Leakage Current HSD2x(ON Power OFF Leakage Current 5.25V, SEL = DYNAMIC CHARACTERISTICS Turn-ON Time ...
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Electrical Specifications - 2.7V to 5.5V Supply PARAMETER Input Voltage High SELH OEH Input Current SELL OEL Input Current SELH Input Current OEH NOTES: 11 Input ...
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Test Circuits and Waveforms VDD LOGIC INPUT 0V SWITCH OUTPUT V OUT 0V FIGURE 2A. MEASUREMENT POINTS V Repeat test for all switches. 7 ISL54220 (Continued) V INPUT 90 Repeat test for all switches. C capacitance. FIGURE 2. ...
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Test Circuits and Waveforms HSDxx IMPEDANCE ANALYZER Dx GND Repeat test for all switches. FIGURE 4. CAPACITANCE TEST CIRCUIT t ri 90% 50% 10% DIN+ t skew_i DIN- 90% 50% 10 90% 10% 50% OUT+ t ...
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Application Block Diagram VBUS D- D+ GND Detailed Description The ISL54220 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 2.7V to 5.5V. ...
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When the range of 2.7V to 5.5V the DD fault voltage will pass through to the output of an active switch channel. The HS1 ...
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In addition when (ground), all switches are DD OFF and the shorted V voltage is isolated from the BUS other side of the switch. When the range of 2.7V to 5.5V, the shorted ...
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Typical Performance Curves V = 3.3V DD FIGURE 11. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH 12 ISL54220 T = +25°C, Unless Otherwise Specified (Continued) A TIME SCALE (0.2ns/DIV) FN6819.1 February 4, 2010 ...
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Typical Performance Curves FIGURE 12. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH 50Ω 0dBm, 0.2VDC BIAS IN 1M 10M FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE 13 ...
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Typical Performance Curves - 50Ω 0dBm, 0.2VDC BIAS IN -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001 0.01 0.1 1M FREQUENCY (Hz) FIGURE 15. CROSSTALK 14 ISL54220 T = +25°C, Unless Otherwise ...
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... Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions ...
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... The pin #1 identifier may be either a mold or mark feature. Maximum package warpage is 0.05mm. 7. Maximum allowable burrs is 0.076mm in all directions. 8. JEDEC Reference MO-255. 9. For additional information, to assist with the PCB Land Pattern 10. Design effort, see Intersil Technical Brief TB389 10X 0. 0. ...
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... Dimensions D2 and E2 are for the exposed pads which provide M 0. improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions TERMINAL TIP ( 2.90 ) MILLIMETERS ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...