IS43DR16320B-25EBL ISSI, Integrated Silicon Solution Inc, IS43DR16320B-25EBL Datasheet - Page 9

• Manufacturer Part Number: IS43DR16320B-25EBL
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16320B-25EBL

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 300mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR86400B, IS43/46DR16320B
DDR2 Extended Mode Register 3 (EMR[3]) Diagram
Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3].
Truth Tables
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
Command Truth Table
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
(Extended) Mode Register
Refresh (REF)
Self Refresh Entry
Sel Refresh Exit
Single Bank Precharge
Precharge All Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
No Operation (NOP)
Device Deselect
Power Down Entry
Power Down Exit
All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
Bank addresses BA0, BA1 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" for details.
The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
“X” means “H or L (but a defined logic level)”
Self refresh exit is asynchronous.
VREF must be maintained during Self Refresh operation.
An refers to the MSBs of addresseses. An=A13 for x8, and An=A12 for x16.
Mode Register
Address Field
Function
Previous
BA1
Cycle
1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
BA0
CKE
1
Current
Cycle
H
H
H
H
H
H
H
H
H
H
H
A13
L
X
X
L
0*
A12
0*
CS#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A11
0*
RAS#
H
H
H
H
H
H
H
H
L
L
L
X
L
L
L
X
X
X
A10
0*
CAS#
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
A9
0*
WE#
H
H
H
H
H
H
H
H
H
L
X
L
L
L
L
X
X
X
A8
0*
A7
BA0-BA1
0*
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
A6
0*
An
A5
0*
(9)
X
X
X
X
X
X
X
X
X
X
X
X
X
-A11
Row Address
A4
0*
Opcode
A10
H
H
H
X
X
X
X
X
X
X
L
L
L
A3
0*
Column 1, 2, 3, 10
Column 1, 2, 3, 10
Column 1, 2, 3, 10
Column 1, 2, 3, 10
A9-A0
X
X
X
X
X
X
X
X
X
A2
0*
A1
0*
Notes
1, 7, 8
1, 2
1, 8
1, 2
1, 2
1, 4
1,4
1
1
1
1
A0
9
0*