PALC22V10B-15PC Cypress Semiconductor Corp, PALC22V10B-15PC Datasheet

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PALC22V10B-15PC

Manufacturer Part Number
PALC22V10B-15PC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of PALC22V10B-15PC

Family Name
Pal®
Process Technology
CMOS
# Macrocells
10
# I/os (max)
10
Frequency (max)
50MHz
Propagation Delay Time
15ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 75C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
24
Package Type
PDIP
Lead Free Status / Rohs Status
Not Compliant

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Cypress Semiconductor Corporation
Document #: 38-03018 Rev. *A
Features
• Advanced second generation PAL architecture
• Low power
• CMOS EPROM technology for reprogrammability
• Variable product terms
• User-programmable macrocell
• Up to 22 input terms and 10 outputs
— 90 mA max. standard
— 100 mA max. military
— 2 x (8 through 16) product terms
— Output polarity control
— Individually selectable for registered or combina-
— 15 ns commercial and industrial
— 15 ns and “20 ns” military
Logic Block Diagram (PDIP/CDIP)
torial operation
10 ns t
10 ns t
15 ns t
50 MHz
10/15 ns t
10/17 ns t
15/20 ns t
50/31 MHz
V SS
13
12
I
CO
S
PD
Reset
CO
S
PD
Macrocell
I/O 9
11
14
I
8
Macrocell
10
I/O 8
10
15
I
Macrocell
This is an abbreviated data sheet. Contact a Cypress
I/O 7
12
16
9
I
representative for complete specifications.
Macrocell
I/O 6
14
17
8
I
3901 North First Street
USE ULTRA37000™ FOR
ALL NEW DESIGNS
Reprogrammable CMOS PAL
Macrocell
7
16
I/O 5
I
18
PROGRAMMABLE
ANDARRAY
(132X 44)
Macrocell
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the “Programmable Macrocell.”
The PALC22V10B is executed in a 24-pin 300-mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic
leadless chip carrier, a 28-lead square plastic leaded chip
carrier, and provides up to 22 inputs and 10 outputs. When the
windowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually
• Enhanced test features
• High reliability
• Windowed DIP, windowed LCC, DIP, LCC, PLCC
I/O 4
16
19
6
I
— Phantom array
— Top test
— Bottom test
— Preload
— Proven EPROM technology
— 100% programming and functional testing
available
Macrocell
14
I/O 3
5
I
20
San Jose
Macrocell
12
I/O 2
4
I
21
,
CA 95134
Macrocell
10
I/O 1
3
22
I
Macrocell
Revised April 22, 2004
PALC22V10B
I/O 0
2
23
I
8
®
408-943-2600
Preset
CP/I
Device
V CC
1
24
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PALC22V10B-15PC Summary of contents

Page 1

... It is implemented with the familiar sum-of-products (AND-OR) logic structure and a new concept, the “Programmable Macrocell.” The PALC22V10B is executed in a 24-pin 300-mil molded DIP, a 300-mil windowed cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides inputs and 10 outputs ...

Page 2

... Cypress against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS PLCC Top View 2827 26 282726 N 121314 1516 1718 PALC22V10B I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 Page [+] Feedback ...

Page 3

... Document History Page Document Title: PALC22V10B Reprogrammable CMOS PAL® Device Document Number: 38-03018 REV. ECN NO. Issue Date ** 106318 05/08/01 *A 213375 See ECN Document #: 38-03018 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change Description of Change SZV Change from Spec number: 38-00195 to 38-03018 FSG Added note to title page: “ ...

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