LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet
LAXP2-17E-5QN208E
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LAXP2-17E-5QN208E Summary of contents
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... LA-LatticeXP2 Family Data Sheet DS1024 Version 01.2, May 2009 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LA-LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... PLLs PFU Blocks The core of the LA-LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro- grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro- grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... Slice Routing PFU BLock Modes Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, ROM 2-3 Architecture LA-LatticeXP2 Family Data Sheet LUT4 & LUT4 LUT4 CARRY Slice PFF Block Resources Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM 2 LUT4s Logic, ROM ...
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... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LA-LatticeXP2 Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...
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... Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives ...
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... Lattice Semiconductor Routing There are many resources provided in the LA-LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU (spans seven PFU) connections ...
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... PLL LOCK to CLKI Clock Dividers LA-LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷ ...
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... LA-LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LA-LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources ...
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... DIV Clock Input Clock Input PLL Input GPLL Note: This diagram shows sources for the LA-LatticeXP2-17 device. Smaller LA-LatticeXP2 devices have two GPLLs. LA-LatticeXP2 Family Data Sheet Clock Input Clock Input From Routing Primary Clock Sources to Eight Quadrant Clock Selection From Routing ...
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... Lattice Semiconductor Secondary Clock/Control Sources LA-LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing ...
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... Input From Routing CLKOP PLL GPLL CLKOS Input Sources for left edge clocks Note: This diagram shows sources for the LA-LatticeXP2-17 device. Smaller LA-LatticeXP2 devices have two GPLLs. LA-LatticeXP2 Family Data Sheet Clock Input Clock Input From From Routing Routing Sources for top ...
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... Lattice Semiconductor Primary Clock Routing The clock routing structure in LA-LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quad- rant ...
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... Lattice Semiconductor LatticeXP2-17. All LA-LatticeXP2 devices have six secondary clock regions and four secondary clocks (SC0 to SC3) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for high fan-out signals ...
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... Secondary Clock Edge Clock Routing LA-LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implemen- tation of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks. ...
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... GPLL Output CLKOP GPLL Output CLKOS sysMEM Memory LA-LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-5 ...
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... Writes to EBR FPGA Logic Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on speci• c design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... The GSR input to the EBR is always asynchronous. Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram Memory Core Programmable Disable LatticeXP2 Memory Usage Reset Clock Clock Enable 2-17 LA-LatticeXP2 Family Data Sheet Port A[17:0] Q SET D L CLR Output Data Latches Port B[17:0] ...
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... General purpose DSP sysDSP Block Capabilities The sysDSP block in the LA-LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LA-LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not ...
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... This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-20 shows the MULT sysDSP element. LA-LatticeXP2 Family Data Sheet x9 x18 ...
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... Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier m Input Data Register Input To Register Multiplier Input To Register Multiplier Shift Register A Out 2-20 Architecture LA-LatticeXP2 Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LA-LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The over• ow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. ...
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... Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-22 Architecture LA-LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST (RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
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... To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-23 Architecture LA-LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-24 Architecture LA-LatticeXP2 Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
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... Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure each DSP module (or group of modules direct HDL instantiation. In addition, Lattice has partnered with The ® MathWorks to support instantiation in the Simulink ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs ...
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... The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. LA-LatticeXP2 Family Data Sheet PIOA IOLT0 ...
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... Output signals from the core for SDR and DDR operation Signals to Tristate Register block for DDR operation Dynamic input delay control bits Tristate signal from the core used in SDR operation Controls signal to the Output block LatticeXP2 High Speed I/O Interface. 2-27 Architecture LA-LatticeXP2 Family Data Sheet Description ...
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... Q D D-Type D-Type DDRSRC SDR & Sync DDR Registers Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-28 Architecture LA-LatticeXP2 Family Data Sheet 2 INCK To DQS Delay Block INDD Clock Transfer Registers IPOS0A QPOS0A D-Type 1 /LATCH D-Type IPOS1A QPOS1A Q D-Type 1 D-Type /LATCH To Routing 2 ...
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... Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKB) DQSXFER * Shared with input register Latch Latch Note: Simplified version does not show CE and SET/RESET details 2-29 Architecture LA-LatticeXP2 Family Data Sheet LatticeXP2 High D-Type 1 /LATCH D-Type Latch DDR Output D Q Registers D-Type /LATCH D-Type ...
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... Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For additional information on using DDR memory support, see TN1138, LatticeXP2 High Speed I/O Interface. 2-30 Architecture LA-LatticeXP2 Family Data Sheet ...
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... Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) DQS Figure 2-29. DQS Input Routing (Top and Bottom) DQS LA-LatticeXP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" ...
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... Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution Spans 16 PIOs Left & Right Sides DQS Input Spans 18 PIOs Top & Bottom Sides LA-LatticeXP2 Family Data Sheet I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 5 ...
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... In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LA-LatticeXP2 family contains dedicated cir- cuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
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... Lattice Semiconductor DQSXFER LA-LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90 signal runs the span of the data bus. sysIO Buffer Each I/O is associated with a • exible buffer referred sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’ ...
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... LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-12 and 2-13 show the I/O standards (together with their supply and reference voltages) supported by LA-LatticeXP2 devices. For further information on utilizing the sysIO buffer to support a variety of standards, see TN1136, sysIO Usage Guide ...
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... Differential SSTL25 Class I, II Differential SSTL33 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS 1. When not specified, V can be set anywhere in the valid operating range (page 3-1). CCIO LA-LatticeXP2 Family Data Sheet V (Nom.) V REF — — — ...
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... These capabilities make the LA-LatticeXP2 ideal for many multiple power supply and hot-swap applications. IEEE 1149.1-Compliant Boundary Scan Testability All LA-LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes ...
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... Guide. flexiFLASH Device Configuration The LA-LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro- gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura- tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141, LatticeXP2 sysCONFIG Usage Guide Figure 2-33 ...
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... Flash portion of the device. Serial TAG Memory LA-LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes, date stamps, asset IDs and calibration settings ...
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... For further information on SED support, see TN1130, On-Chip Oscillator Every LA-LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for con- figuration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the design process, the following sequence takes place: 1 ...
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... Lattice Semiconductor Density Shifting The LA-LatticeXP2 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...
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... Data Retention RETENTION © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... CCIO V = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3-2 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Min. Typ. Max. — — +/- and CCAUX CCIO Min. Typ. Max. — — 10 — — 150 -30 — ...
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... Over Recommended Operating Conditions Parameter LA-XP2-5 LA-XP2-8 LA-XP2-17 LA-XP2-5 6 LA-XP2-8 LA-XP2-17 Power Estimation and Management for LatticeXP2 For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary 3-3 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet 5 Device Typical 14 18 ...
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... Over Recommended Operating Conditions Parameter LA-XP2-5 LA-XP2-8 LA-XP2-17 LA-XP2-5 7 LA-XP2-8 LA-XP2-17 Power Estimation and Management for LatticeXP2 For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary CCPLL. 3-4 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Typical 6 Device (25° ...
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... Over Recommended Operating Conditions Parameter Device LA-XP2-5 LA-XP2-8 LA-XP2-17 LA-XP2-5 7 LA-XP2-8 LA-XP2-17 8 Power Estimation and Management for LatticeXP2 . For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary 3-5 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Typical 6 (25°C, Max. Supply ...
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... CCIO 3-6 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet V (V) REF Min. Typ. — — — — — — — — — — — — — ...
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... REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-7 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 ...
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... LVDS25E The top and bottom sides of LA-LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. ...
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... I/O bank with 3.3V VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Description Typical 2.50 ...
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... Lattice Semiconductor BLVDS The LA-LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LA-LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using comple- mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
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... Lattice Semiconductor RSDS The LA-LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LA-LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... Multiplier (All Registers) 36x36 Multiply (All Registers) 18x18 Multiply/Accumulate (Input and Output Registers) 18x18 Multiply-Add/Sub-Sum (All Registers) Over Recommended Operating Conditions Function Function 3-14 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet 1 -5 Timing 5.7 6.9 7.7 4.8 5.1 5.6 5.8 ...
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... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Function 3-15 -5 Timing ...
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... General I/O Pin Parameters (using Primary Clock with PLL) t Clock to Output - PIO Output Register COPLL t Clock to Data Setup - PIO Input Register SUPLL Over Recommended Operating Conditions Description 3-16 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet -5 Device Min. Max. LA-XP2-5 — 4.77 LA-XP2-8 — 4.77 LA-XP2-17 — 4.78 LA-XP2-5 -0 ...
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... Lattice Semiconductor LA-LatticeXP2 External Switching Characteristics (Continued) Parameter t Clock to Data Hold - PIO Input Register HPLL t Clock to Data Setup - PIO Input Register with Data Input Delay SU_DELPLL t Clock to Data Hold - PIO Input Register with Input Data Delay H_DELPLL 2 3 DDR and DDR2 ...
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... Setup Address to EBR Memory (Write Clk) SUADDR_EBR t Hold Address to EBR Memory (Write Clk) HADDR_EBR t Setup Write/Read Enable to EBR Memory (Write/Read Clk) SUWREN_EBR Over Recommended Operating Conditions Description 3-18 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet 1 -5 Min. Max. — 0.275 — 0.522 — 0.865 0.156 — ...
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... Internal parameters are characterized, but not tested on every device. 2. RST resets VCO and all counters in PLL. 3. These parameters include the Adder Subtractor block in the path. Timing v. A 0.12 Over Recommended Operating Conditions Description 3-19 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet 1 (Continued) -5 Min. Max. 0.217 — ...
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... Figure 3-7. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Invalid Data Mem(n) data from previous read output is only updated during a read cycle 3-20 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
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... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-21 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet ACCESS ...
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... LVPECL 3.3 HSTL18_I HSTL_18 class I 8mA drive HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I 8mA drive HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 3-22 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet -5 Units 0.05 ns 0.05 ns 0.05 ns 0.05 ns 0.05 ns 0.07 ns 0. ...
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... LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-23 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet -5 Units 1.11 ns 1.11 ns 0.37 ns 0.29 ns ...
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... LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing (Continued) Over Recommended Operating Conditions Description 3-24 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet -5 Units 1.60 ns 1.40 ns 1. ...
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... MHz < f < 400 MHz OUT f < 100 MHz OUT N/M = integer At 90 435MHz 10 to 25MHz 90% to 90% 10% to 10% 10% to 90% 3-25 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Min. Typ. Max. 10 — 435 10 — 435 0.078 — 217.5 3.3 — ...
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... Lattice Semiconductor LA-LatticeXP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG POR, Initialization and Wake Up t Minimum Vcc to INITN High ICFG t Time from tICFG to valid Master CCLK VMC t PROGRAMN Pin Pulse Rejection PRGMRJ t PROGRAMN Low Time to Start Con• guration PRGM t PROGRAMN High to INITN High Delay ...
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... VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI Over Recommended Operating Conditions Min. Selected value -30% Selected value +30% 40 Capture CFGx … Opcode 3-27 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Max. Units MHz … … 127 128 Address Ignore Valid Bitstream ...
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... Main Array TAG Main Array TAG Main Array Over Recommended Operating Conditions EBR Density (Bits) Time (Typ.) 166K 221K 276K 3-28 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Min. Typ. Max. — 1.8 2.1 — 1.9 2.3 — 1.7 2.0 — ...
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... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-29 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Min. Max. — — 20 — 20 — 8 — 10 — 50 — — 10 — 10 — — 25 — — 25 — 25 — ...
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... Includes Test Fixture and Probe Capacitance 1M¾ 1M¾ 100 100 3-30 DC and Switching Characteristics LA-LatticeXP2 Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
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... TCK TDI © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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... Chip select in Slave SPI mode. This pin has a weak internal pull-up. Test Output Enable tristates all I/O pins when driven low. This pin has a weak I internal pull-up, but when not used an external pull- mended. 4-2 Pinout Information LA-LatticeXP2 Family Data Sheet Description is recom- CC ...
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... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LA-LatticeXP2 Family Data Sheet DDR Strobe (DQS) and PIO Within PIC Data (DQ) Pins ...
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... Pinout Information LA-LatticeXP2 Family Data Sheet LA-XP2-8 132 144 208 256 208 TQFP PQFP ftBGA PQFP 86 100 146 201 146 ...
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... Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the specific thermal values. For Further Information • TN1139 - Power Estimation and Management for LatticeXP2 Devices • Power Calculator tool included with Lattice ispLEVER software standalone download from www.latticesemi.com/software LA-XP2-5 132 144 208 ...
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... May 2009 Part Number Description LAXP2 – – 5 XXXXX X Device Family LA-XP2 Automotive FPGA Logic Capacity LUTs LUTs 17 = 17K LUTs Supply Voltage E = 1.2V Speed Ordering Information The LA-LatticeXP2 devices are marked with a single automotive temperature grade, as shown below. Automotive Disclaimer Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for use in applications related to the deployment of airbags ...
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... LAXP2-5E-5TN144E 1.2V LAXP2-5E-5QN208E 1.2V LAXP2-5E-5FTN256E 1.2V Part Number Voltage LAXP2-8E-5MN132E 1.2V LAXP2-8E-5TN144E 1.2V LAXP2-8E-5QN208E 1.2V LAXP2-8E-5FTN256E 1.2V Part Number Voltage LAXP2-17E-5QN208E 1.2V LAXP2-17E-5FTN256E 1.2V LA-LatticeXP2 Family Data Sheet Grade Package Pins -5 Lead-Free csBGA 132 -5 Lead-Free TQFP 144 -5 Lead-Free PQFP 208 -5 Lead-Free ftBGA ...
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... PCI: www.pcisig.com © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Pinout Information Ordering Informtion © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...