LFX125EB-04F256I Lattice, LFX125EB-04F256I Datasheet
LFX125EB-04F256I
Specifications of LFX125EB-04F256I
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LFX125EB-04F256I Summary of contents
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... FH516 package was converted to F516 via PCN# 09A-08. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The tool also provides outputs to common timing analysis tools for timing analysis. To increase designer productivity, Lattice provides a variety of pre-designed modules referred cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces, and memory controllers ...
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... Lattice Semiconductor Architecture Overview The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units (PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib- uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO blocks, each of which includes one input and output buffer ...
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... Lattice Semiconductor Figure 1. ispXPGA Block Diagram Programmable Function Unit The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen- erator (WLG) ...
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... Lattice Semiconductor Figure 2. ispXPGA PFU OE PFUCLK0 Control PFUCLK1 Logic CEB0 CEB1 SR WIN0 WIN1 LUT-4 WIN2 WIN3 SEL0 XIN0 XIN1 LUT-4 XIN2 XIN3 SEL0 SEL1 YIN0 YIN1 LUT-4 YIN2 YIN3 SEL2 ZIN0 ZIN1 LUT-4 ZIN2 ZIN3 SEL3 COUT(r,c) COUT WLGW0 4A COUT S3 LUT-4 SUM ...
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... Lattice Semiconductor Configurable Logic Element The CLE is made four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder, and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of the AND gate to one of the inputs of the CCG. Of the fi ...
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... Lattice Semiconductor Figure 4. LUT in Shift Register Mode SEL (SHIFTIN) Carry Chain Generator The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a two- input XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0 ...
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... Lattice Semiconductor Figure 6. ispXPGA Wide Logic Generator COUT WIN2 WIN3 4A S3 SEL0 4B XIN2 XIN3 S2 SEL1 SEL3 4C SEL2 4D YIN2 YIN3 S1 ZIN2 ZIN3 S0 Configurable Sequential Element There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in implementing effi ...
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... Lattice Semiconductor Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not controllable inside the PFU. The polarity of the Global Set/Reset signal (GSR) is programmable. Figure 9 shows the Clock Enable and Output Enable selection for each PFU ...
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... Lattice Semiconductor Figure 10. ispXPGA PIC sysIO From routing From sysHSI block To sysHSI block Only for PICs associated with sysHSI blocks From sysHSI block To sysHSI block From routing sysIO Programmable Input/Output The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are generated from routing ...
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... Lattice Semiconductor Figure 11. ispXPGA PIO From sysHSI block From sysHSI block Feed-through (FT) From sysIO Input Clock (CLK) Input Clock Enable (ICEN) Input Set/Reset (ISR) Global Set/Reset(GSR) PIO Input (IN) Output Clock Enable (OCEN) Output Set/Reset (OSR) PIO Output Enable(OEN) PIO Input Enable (IEN) ...
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... Lattice Semiconductor Memory The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see Look- Up Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM or ROM. Additionally, the internal logic of the device can be used to confi ...
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... Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15 illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note num- ber TN1028 ispXPGA Memory Usage Guidelines, available at www.latticesemi.com. ...
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... The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the PLL. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL Usage and Design Guidelines, available at www.latticesemi.com. ...
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... Lattice Semiconductor Figure 17. ispXPGA PLL_RST and PLL_FBK Generation Clock Routing The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illus- trates the generation of the Global Clock Lines. Figure 18. Global Clock Line Generation GCLK0 CLK_OUT0 ...
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... I/O pins to create the differential pair. The logic level is determined by the difference in the two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices. For more information on sysIO capability, refer to Lattice technical note number TN1000, sysIO Usage Guidelines for Lattice Devices available at www.latticesemi.com. ...
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... Supported with external resistor network BLVDS Receiver Supported (may need termination) Driver Supported with external resistor network LVPECL Receiver Supported with termination 1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines, available at www.latticesemi.com. V CCO 3.3V 3.3V 2.5V 1.8V 3.3V 3.3V 3 ...
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... Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 chan- nels. For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guide- lines. Figure 20. sysHSI Block Diagram ...
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... E mode. Additionally, the SRAM can be re-configured from the E Lattice technical note number TN1026, ispXP Configuration Usage Guide, for more in depth information on the dif- ferent programming modes, timing and wake-up, available at www.latticesemi.com. Figure 21. ispXP Block Diagram ...
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... The temperature-sensing diode works for the entire operating range as shown in Figure 22 - Sensing Diode Volt- age-Temperature Relationship. Refer to Lattice’s Thermal Management document for thermal coefficients. Also refer to Lattice technical note number TN1043, Power Estimation in ispXPGA Devices. Figure 22. Sensing Diode Voltage-Temperature Relationship ...
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... Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications). 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of - ...
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... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Low Leakage IL IH Input High Leakage Current I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold Low Sustaining Current V BHLS I Bus Hold High Sustaining Current V BHHS I Bus Hold Low Overdrive Current ...
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... T = 25˚C, frequency = 1.0 MHz, device configured with 16-bit counters varies with specific device configuration and operating frequency. For more accurate power calculation, see Lattice technical note num- CC ber TN1043, Power Estimation in ispXPGA Devices 25˚C, per bank load, frequency = 0 MHz. ...
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... Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.0 LVCMOS 2.5 2.3 2 LVCMOS 1.8 1.65 LVTTL 3.0 PCI 3.3 3.0 AGP-1X 3.15 SSTL 2 2.3 SSTL 3 3.0 CTT 3.3 3.0 CTT 2.5 2.3 HSTL Class I 1.4 HSTL Class III 1.4 ...
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... Lattice Semiconductor sysIO DC Electrical Characteristics V IL Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVCMOS 2.5 -0.3 0.7 0.68 1 LVCMOS 1.8 -0.3 0.35V LVTTL -0.3 0.8 1.08 PCI 3.3 -0.3 0.3V 1.08 AGP-1X -0.3 0.3 V SSTL 3 Class I -0.3 V REF SSTL 3 Class II -0.3 ...
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... Between H and Output Voltage Offset OS Change in V Between H and L Δ Output Short Circuit Current OSD 1. Refer to Lattice technical note TN1000, sysIO Usage Guidelines for Lattice Devices and V are the two outputs of the LVDS/BLVDS output buffer LVPECL DC Parameter Parameter Description V CCO V Input Voltage High ...
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... Lattice Semiconductor Figure 23. LVPECL Driver with Three Resistor Pack ispXPLD Emulated LVPECL Buffer ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characteristics Parameter Description Global Clock Input Output t Global Clock Input Setup S t Global Clock Input Hold H t Global Clock Input Setup ...
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... Lattice Semiconductor ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters Parameter Functional Delays LUTs t 4-Input LUT Delay LUT4 t 5-Input LUT Delay LUT5 t 6-Input LUT Delay LUT6 Shift Register (LUT) t Shift Register Setup Time LSR_S t Shift Register Hold Time LSR_H t Shift Register Clock to Output Delay ...
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... Lattice Semiconductor ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters (Cont.) Parameter Reset/Set t Asynchronous Set/Reset to Output LASSRO t Asynchronous Set/Reset Pulse Width LASSRPW t Asynchronous Set/Reset Recovery LASSRR t Synchronous Set/Reset Setup Time LSSR_S t Synchronous Set/Reset Hold Time LSSR_H 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. ...
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... Lattice Semiconductor ispXPGA 125B/C & ispXPGA 125EB/EC EBR Timing Parameters Parameter Synchronous Write t Address Setup Delay EBSWAD_S t Address Hold Delay EBSWAD_H t Clock Pulse Width EBSWCPW t Write Enable Setup Time EBSWWE_S t Write Enable Hold Time EBSWWE_H t Data Setup Time EBSWD_S t Data Hold Time ...
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... Lattice Semiconductor ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders Parameter Optional Adders t Input Delay IOINDLY t Input Adjusters IOI LVTTL_in Using 3.3V TTL LVCMOS_18_in Using 1.8V CMOS LVCMOS_25_in Using 2.5V CMOS LVCMOS_33_in Using 3.3V CMOS AGP_1X_in Using AGP 1x CTT25_in Using CTT 2.5V CTT33_in Using CTT 3 ...
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... Lattice Semiconductor ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders (Cont.) Parameter LVCMOS_33_4mA_out Using 3.3V CMOS Standard, 4mA Drive LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive LVCMOS_33_16mA_out Using 3.3V CMOS Standard, ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC External Switching Characteristics Parameter Description Global Clock Input to Out put t Global Clock Input Setup S t Global Clock Input Hold H t Global Clock Input Setup SINDLY t Global Clock Input Hold HINDLY Global Clock Input to t COPLL ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters Parameter Functional Delays LUTs t 4-Input LUT Delay LUT4 t 5-Input LUT Delay LUT5 t 6-Input LUT Delay LUT6 Shift Register (LUT) t Shift Register Setup Time LSR_S t Shift Register Hold Time LSR_H t Shift Register Clock to Output Delay ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters (Cont.) Parameter Reset/Set t Asynchronous Set/Reset to Output LASSRO t Asynchronous Set/Reset Pulse Width LASSRPW t Asynchronous Set/Reset Recovery LASSRR t Synchronous Set/Reset Setup Time LSSR_S t Synchronous Set/Reset Hold Time LSSR_H 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC EBR Timing Parameters Parameter Synchronous Write t Address Setup Delay EBSWAD_S t Address Hold Delay EBSWAD_H t Clock Pulse Width EBSWCPW t Write Enable Setup Time EBSWWE_S t Write Enable Hold Time EBSWWE_H t Data Setup Time EBSWD_S t Data Hold Time ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders Parameter Optional Adders t Input Delay IOINDLY t Input Adjusters IOI LVTTL_in Using 3.3V TTL LVCMOS_18_in Using 1.8V CMOS LVCMOS_25_in Using 2.5V CMOS LVCMOS_33_in Using 3.3V CMOS AGP_1X_in Using AGP 1x CTT25_in Using CTT 2.5V CTT33_in Using CTT 3 ...
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... Lattice Semiconductor ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders (Cont.) Parameter LVCMOS_33_4mA_out Using 3.3V CMOS Standard, 4mA Drive LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive LVCMOS_33_16mA_out Using 3.3V CMOS Standard, ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC External Switching Characteristics Parameter Description Global Clock Input to Out put t Global Clock Input Setup S t Global Clock Input Hold H t Global Clock Input Setup SINDLY t Global Clock Input Hold HINDLY Global Clock Input to t COPLL ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters Parameter Functional Delays LUTs t 4-Input LUT Delay LUT4 t 5-Input LUT Delay LUT5 t 6-Input LUT Delay LUT6 Shift Register (LUT) t Shift Register Setup Time LSR_S t Shift Register Hold Time LSR_H t Shift Register Clock to Output Delay ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters (Cont.) Parameter Reset/Set t Asynchronous Set/Reset to Output LASSRO t Asynchronous Set/Reset Pulse Width LASSRPW t Asynchronous Set/Reset Recovery LASSRR t Synchronous Set/Reset Setup Time LSSR_S t Synchronous Set/Reset Hold Time LSSR_H 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC EBR Timing Parameters Parameter Synchronous Write t Address Setup Delay EBSWAD_S t Address Hold Delay EBSWAD_H t Clock Pulse Width EBSWCPW t Write Enable Setup Time EBSWWE_S t Write Enable Hold Time EBSWWE_H t Data Setup Time EBSWD_S t Data Hold Time ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders Parameter Optional Adders t Input Delay IOINDLY t Input Adjusters IOI LVTTL_in Using 3.3V TTL LVCMOS_18_in Using 1.8V CMOS LVCMOS_25_in Using 2.5V CMOS LVCMOS_33_in Using 3.3V CMOS AGP_1X_in Using AGP 1x CTT25_in Using CTT 2.5V CTT33_in Using CTT 3 ...
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... Lattice Semiconductor ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders (Cont.) Parameter LVCMOS_33_4mA_out Using 3.3V CMOS Standard, 4mA Drive LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive LVCMOS_33_16mA_out Using 3.3V CMOS Standard, ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC External Switching Characteristics Parameter Description Global Clock Input to Out put t Global Clock Input Setup S t Global Clock Input Hold H t Global Clock Input Setup SINDLY t Global Clock Input Hold HINDLY Global Clock Input to t COPLL ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters Parameter Functional Delays LUTs t 4-Input LUT Delay LUT4 t 5-Input LUT Delay LUT5 t 6-Input LUT Delay LUT6 Shift Register (LUT) t Shift Register Setup Time LSR_S t Shift Register Hold Time LSR_H t Shift Register Clock to Output Delay ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters (Cont.) Parameter Reset/Set t Asynchronous Set/Reset to Output LASSRO t Asynchronous Set/Reset Pulse Width LASSRPW t Asynchronous Set/Reset Recovery LASSRR t Synchronous Set/Reset Setup Time LSSR_S t Synchronous Set/Reset Hold Time LSSR_H 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC EBR Timing Parameters Parameter Synchronous Write t Address Setup Delay EBSWAD_S t Address Hold Delay EBSWAD_H t Clock Pulse Width EBSWCPW t Write Enable Setup Time EBSWWE_S t Write Enable Hold Time EBSWWE_H t Data Setup Time EBSWD_S t Data Hold Time ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders Parameter Optional Adders t Input Delay IOINDLY t Input Adjusters IOI LVTTL_in Using 3.3V TTL LVCMOS_18_in Using 1.8V CMOS LVCMOS_25_in Using 2.5V CMOS LVCMOS_33_in Using 3.3V CMOS AGP_1X_in Using AGP 1x CTT25_in Using CTT 2.5V CTT33_in Using CTT 3 ...
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... Lattice Semiconductor ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders (Cont.) Parameter LVCMOS_33_4mA_out Using 3.3V CMOS Standard, 4mA Drive LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive LVCMOS_33_16mA_out Using 3.3V CMOS Standard, ...
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... Lattice Semiconductor sysHSI Block Timing Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Figure 24. Receive Data Eye Diagram Template (Differential) ...
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... Lattice Semiconductor sysHSI Block AC Specifications Symbol Description Mode SS:CAL Reference Clock f 10B12B CLK Frequency 8B10B SS:CAL 2 f Serial Input 10B12B SIN 8B10B 2 f Serial Out LVDS OUT 1. Only available for ispXPGA 125B, 200B, 500B and 1200B (2.5V/3.3V) devices and f speeds are supported at V ...
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... Lattice Semiconductor REFCLK and SS_CLKIN Timing Symbol Description Frequency Deviation Between TX REFCLK and t DREFCLK CDRX REFCLK on One Link t REFCLK, SS_CLKIN Peak-to-Peak Period Jitter JPPREFCLK REFCLK, SS_CLKIN Pulse Width, (80 20% to 20%). PWREFCLK REFCLK, SS_CLKIN Rise/Fall Time (20 RFREFCLK 80% to 20%) 2 Serializer Timing ...
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... Lattice Semiconductor Lock-in Timing CDRX_SS LOCK-IN (DE-SKEW) TIMING SIN CAL SYDT RXD(0:7) CDR_10B12B LOCK-IN TIMING SIN SYDT RXD(0:9) CDR_8B10B LOCK-IN TIMING SI N SYDT RXD(0:9) SYDT Timing SYDT TIMING FOR CDRX_10B12B RECCLK SYDT RXD(0:9) SYDT TIMING FOR CDRX_8B10B RECCLK SYDT RXD(0:9) MIN. 1200 SYNCPAT DATA (SERIAL ) MIN ...
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... Lattice Semiconductor Serializer Timing 8B/10B SERIALIZER DELAY TIMING TXD REFCLK SOUT SYMBOL N-1 10B/12B SERIALIZER DELAY TIMING TXD REFCLK SOUT SS Mode SERIALIZER DELAY TIMING TXD REFCLK SS_CLKOUT b4 SOUT SYMBOL N-1 INTERNAL TIMING FOR sysHSI BLOCK RECCLK SYDT, RXD SYMBOL N t COSOUT ...
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... Lattice Semiconductor Deserializer Timing 8B/10B DESERIALIZER DELAY TIMING SYMBOL SIN RECCLK RXD 10B/12B DESERIALIZER DELAY TIMING SYMBOL N SIN "1" RECCLK RXD SYMBOL N-2 CDRX_SS DESERIALIZER DELAY TIMING SYMBOL SIN RECCLK SYMBOL N-2 RXD INTERNAL TIMING FOR sysHSI BLOCK REFCLK t HSITXDDATAS TXD ...
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... Lattice Semiconductor sysCLOCK PLL Timing Symbol Parameter t Input clock, high time PWH t Input clock, low time PWL Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) INSTB f M Divider input, frequency range MDIVIN f M Divider output, frequency range ...
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... Lattice Semiconductor ispXP sysCONFIG Port Timing Specifications Symbol sysCONFIG Write Cycle Timing t Input setup time CCLK rise SUCS t Hold time CCLK Rise HCS t Input setup time of write data to CCLK rise SUWD t Hold time of write data to CCLK rise HWD t Low time to reset device SRAM ...
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... Lattice Semiconductor Switching Test Conditions Figure 25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 7. Figure 25. Output Test Load, LVTTL and LVCMOS Standards Device Output *C Table 7. Text Fixture Required Components Test Condition LVCMOS I/O, (L -> ...
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... Lattice Semiconductor 1 Signal Descriptions Signal Name General Purpose 1,2 BKy_IOx 7 n GCLK /In GSR NC GND CCJ 2 V CCOy 2 V REFy D D XN, XP Test and Program/Configuration TMS TCK TDI TDO TOE CFG0 PROGRAMb DONE INITb READ CCLK CSb DATA[0:7] 3 sysCLOCK PLL PLL_FBKz ...
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... Lattice Semiconductor 1 Signal Descriptions (Cont.) Signal Name HSImA_CDRRST, HSImB_CDRRST HSIm_CSLOCK, HSIm_CSLOCK sysHSI Block (Source Synchronous Mode) SS_CLKIN0P, SS_CLKIN1P SS_CLKIN0N, SS_CLKIN1N SS_CLKOUT0P, SS_CLKOUT1P SS_CLKOUT0N, SS_CLKOUT1N CAL0, CAL1 variable for the I/O number variable for the I/O Bank variable for the PLL number. ...
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... Lattice Semiconductor ispXPGA Power Supply and NC Connections Signal 256-Ball fpBGA V C3, C14, D4, D13, E5, E12, F6, F11, CC L6, L11, M5, M12, N4, N13, P3, P14 V F5, G5 CCO0 V K5, L5 CCO1 V M6, M7 CCO2 V M10, M11 CCO3 V K12, L12 CCO4 V G12, F12 CCO5 V E10, E11 CCO6 V E6, E7 CCO7 V H3, J15 ...
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... Lattice Semiconductor ispXPGA Power Supply and NC Connections Signal 680-Ball fpBGA V AE35, AE5, AL5, AR15, AR25, AR31, AR35, AR5, CC AT36, AT4, AU3, AU37, C3, C37, D36, D4, E15, E25, E35, E5, E9, J35, R35 E11, E12, E13, E17, E18, E7 CCO0 V E22, E23, E27, E29, E31, E33 ...
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... Lattice Semiconductor ispXPGA Power Supply and NC Connections Signal 680-Ball fpBGA 2 NC A3, B29, AW3, AV3, AW11, AV11, AV29, AW29, AW37, B3, AV37, C39, C38, AU39, AU38, AJ39, AJ38, N38, N39, C2, C1, AU1, AU2, AJ2, AJ1, N2, N1, B11, A11, A37, B37, A29 1. All grounds must be electrically connected at the board level. ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA 256-fpBGA Second Ball Signal Name Function C2 BK0_IO2 HSI0A_SOUTP - GND (Bank 0) D2 BK0_IO3 HSI0A_SOUTN B1 BK0_IO6 HSI0A_SINP - - C1 BK0_IO7 HSI0A_SINN D3 BK0_IO8 E3 BK0_IO9 VREF0 D1 BK0_IO10 HSI0B_SOUTP - GND (Bank 0) E1 BK0_IO11 HSI0B_SOUTN E2 BK0_IO12 F2 BK0_IO13 F1 BK0_IO14 HSI0B_SINP - - G1 BK0_IO15 HSI0B_SINN ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) 256-fpBGA Second Ball Signal Name Function - GND (Bank 1) L3 BK1_IO7 SS_CLKIN0N K2 BK1_IO8 - - L2 BK1_IO9 M1 BK1_IO10 HSI1A_SOUTP N1 BK1_IO11 HSI1A_SOUTN M3 BK1_IO12 PLL_RST2 M4 BK1_IO13 PLL_RST3 - GND (Bank BK1_IO16 VREF1 P1 BK1_IO18 HSI1B_SOUTP - - R1 BK1_IO19 HSI1B_SOUTN 1 N3 BK1_IO20 N2 BK1_IO22 ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) 256-fpBGA Second Ball Signal Name Function - GND (Bank 2) R8 BK2_IO19 N8 BK2_IO20 P8 BK2_IO21 - GND (Bank 2) - GND (Bank 3) T8 BK3_IO0 T9 BK3_IO1 R9 BK3_IO2 - - R10 BK3_IO3 P9 BK3_IO4 N9 BK3_IO5 T10 BK3_IO6 - GND (Bank 3) T11 BK3_IO7 P10 BK3_IO8 ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) 256-fpBGA Second Ball Signal Name Function M15 BK4_IO5 M14 BK4_IO8 M13 BK4_IO9 VREF4 - GND (Bank 4) L13 BK4_IO12 PLL_RST4 L14 BK4_IO13 PLL_RST5 N16 BK4_IO14 HSI2B_SOUTP M16 BK4_IO15 HSI2B_SOUTN - - L15 BK4_IO18 SS_CLKIN1P - GND (Bank 4) ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) 256-fpBGA Second Ball Signal Name Function D16 BK5_IO15 HSI3A_SOUTN E13 BK5_IO16 VREF5 E14 BK5_IO17 E15 BK5_IO18 HSI3B_SINP - - D15 BK5_IO19 HSI3B_SINN C16 BK5_IO22 HSI3B_SOUTP - GND (Bank 5) B16 BK5_IO23 HSI3B_SOUTN D14 BK5_IO24 C15 BK5_IO25 ...
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... Lattice Semiconductor ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) 256-fpBGA Second Ball Signal Name Function C8 BK7_IO1 B8 BK7_IO2 B7 BK7_IO3 A9 BK7_IO6 - GND (Bank 7) A8 BK7_IO7 C7 BK7_IO10 D7 BK7_IO11 D6 BK7_IO12 - - C6 BK7_IO13 B6 BK7_IO14 - GND (Bank 7) B5 BK7_IO15 A7 BK7_IO16 VREF7 A6 BK7_IO17 D5 BK7_IO18 C5 BK7_IO19 A5 BK7_IO20 - - A4 BK7_IO21 B4 BK7_IO22 - GND (Bank 7) ...
Page 71
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA LFX500 516-Ball Second BGA Ball Signal Name Function E4 BK0_IO0 - D3 BK0_IO1 - E3 BK0_IO2 HSI0A_SOUTP - GND (Bank BK0_IO3 HSI0A_SOUTN C2 BK0_IO4 - B1 BK0_IO5 - G4 BK0_IO6 HSI0A_SINP - - - G3 BK0_IO7 HSI0A_SINN C1 BK0_IO8 - D2 BK0_IO9 VREF0 H4 BK0_IO10 HSI0B_SOUTP - GND (Bank BK0_IO11 HSI0B_SOUTN D1 BK0_IO12 - E1 BK0_IO13 ...
Page 72
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function - - - R2 GCLK0 - R3 GCLK1 - R4 VCCP0 - T4 GNDP0 - T3 GCLK2 - T2 GCLK3 - - - - T1 BK1_IO0 CLK_OUT2 - GND (Bank BK1_IO1 CLK_OUT3 U2 BK1_IO2 SS_CLKOUT0P - - - U3 BK1_IO3 SS_CLKOUT0N V1 BK1_IO4 PLL_FBK2 V2 BK1_IO5 PLL_FBK3 V3 BK1_IO6 - - GND (Bank BK1_IO7 ...
Page 73
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function AE3 BK1_IO33 - AG1 BK1_IO34 - AH1 BK1_IO35 - AG2 BK1_IO36 - AF3 BK1_IO37 - AJ1 BK1_IO38 - - GND (Bank 1) - AH2 BK1_IO39 - AG3 BK1_IO40 - AF4 BK1_IO41 - AK2 TCK - AJ3 TMS ...
Page 74
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function AJ13 BK2_IO32 - - - - AK12 BK2_IO33 - AK13 BK2_IO34 - - GND (Bank 2) - AH14 BK2_IO35 - AJ14 BK2_IO36 - AK14 BK2_IO37 - AG15 BK2_IO38 - AH15 BK2_IO39 - AJ15 BK2_IO40 - AK15 BK2_IO41 - - GND (Bank 2) ...
Page 75
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function AJ25 BK3_IO32 - AG24 BK3_IO33 - AK26 BK3_IO34 - - - - AH25 BK3_IO35 - AJ26 BK3_IO36 - - - - AH26 BK3_IO37 - AK27 BK3_IO38 - - GND (Bank 3) - AJ27 BK3_IO39 - AG26 BK3_IO40 - AH27 BK3_IO41 - AK28 GSR ...
Page 76
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function AA30 BK4_IO29 - W28 BK4_IO30 SS_CLKIN1P - - - W29 BK4_IO31 SS_CLKIN1N Y30 BK4_IO32 - W30 BK4_IO33 - V27 BK4_IO34 - - GND (Bank 4) - V28 BK4_IO35 - V29 BK4_IO36 PLL_FBK4 V30 BK4_IO37 PLL_FBK5 ...
Page 77
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function J29 BK5_IO22 HSI4B_SOUTP - GND (Bank 5) - H29 BK5_IO23 HSI4B_SOUTN F30 BK5_IO24 - G29 BK5_IO25 - H28 BK5_IO26 HSI5A_SINP H27 BK5_IO27 HSI5A_SINN E30 BK5_IO28 - F29 BK5_IO29 - G28 BK5_IO30 ...
Page 78
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function D21 BK6_IO20 - C21 BK6_IO21 VREF6 B21 BK6_IO22 DATA5 - - - A21 BK6_IO23 DATA4 D20 BK6_IO24 - - - - C20 BK6_IO25 - B20 BK6_IO26 DATA3 - GND (Bank 6) - A20 BK6_IO27 DATA2 C19 ...
Page 79
... Lattice Semiconductor ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 516-Ball Second BGA Ball Signal Name Function A10 BK7_IO18 - B10 BK7_IO19 - C10 BK7_IO20 VREF7 D10 BK7_IO21 - B9 BK7_IO22 - - GND (Bank BK7_IO23 - A8 BK7_IO24 - - - - B8 BK7_IO25 - C8 BK7_IO26 - D8 BK7_IO27 - A7 BK7_IO28 - B7 BK7_IO29 - C7 BK7_IO30 - - GND (Bank BK7_IO31 - A6 BK7_IO32 ...
Page 80
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA 680-Ball fpBGA Signal Name C4 BK0_IO0 B4 BK0_IO1 E6 BK0_IO2 - GND (Bank 0) D6 BK0_IO3 A4 BK0_IO4 E8 BK0_IO5 C5 BK0_IO6 C6 BK0_IO7 A6 BK0_IO8 A5 BK0_IO9 B6 BK0_IO10 - GND (Bank 0) B5 BK0_IO11 B7 BK0_IO12 A7 BK0_IO13 D8 BK0_IO14 D7 BK0_IO15 D9 BK0_IO16 E10 BK0_IO17 C8 BK0_IO18 - GND (Bank 0) C7 ...
Page 81
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name D14 BK0_IO37 C13 BK0_IO38 D13 BK0_IO39 B14 BK0_IO40 A14 BK0_IO41 C15 BK0_IO42 - GND (Bank 0) D15 BK0_IO43 A15 BK0_IO44 C16 BK0_IO45 B15 BK0_IO46 B16 BK0_IO47 A16 BK0_IO48 B17 BK0_IO49 ...
Page 82
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name C24 BK1_IO7 A22 BK1_IO8 D22 BK1_IO9 A23 BK1_IO10 - GND (Bank 1) B25 BK1_IO11 D23 BK1_IO12 A24 BK1_IO13 A25 BK1_IO14 E24 BK1_IO15 D24 BK1_IO16 A26 BK1_IO17 D25 BK1_IO18 - GND (Bank 1) ...
Page 83
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name A33 BK1_IO45 C33 BK1_IO46 B33 BK1_IO47 A34 BK1_IO48 A35 BK1_IO49 D32 BK1_IO50 - GND (Bank 1) D33 BK1_IO51 E32 BK1_IO52 C34 BK1_IO53 B34 BK1_IO54 B35 BK1_IO55 A36 BK1_IO56 D34 BK1_IO57 ...
Page 84
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name - GND (Bank 2) K36 BK2_IO19 H38 BK2_IO20 J38 BK2_IO21 J39 BK2_IO22 L36 BK2_IO23 K38 BK2_IO24 M36 BK2_IO25 L37 BK2_IO26 - GND (Bank 2) K39 BK2_IO27 L38 BK2_IO28 P35 BK2_IO29 N36 BK2_IO30 ...
Page 85
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name V39 BK2_IO57 W37 BK2_IO58 - GND (Bank 2) W38 BK2_IO59 W39 BK2_IO60 AA39 BK2_IO61 - GND (Bank 2) - GND (Bank 3) AA38 BK3_IO0 Y35 BK3_IO1 AA37 BK3_IO2 - GND (Bank 3) AA35 BK3_IO3 AB39 BK3_IO4 ...
Page 86
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name AH39 BK3_IO31 AK39 BK3_IO32 AK38 BK3_IO33 AF35 BK3_IO34 - GND (Bank 3) AJ37 BK3_IO35 AH36 BK3_IO36 AM39 BK3_IO37 AL38 BK3_IO38 AL39 BK3_IO39 AJ36 BK3_IO40 AH35 BK3_IO41 AL37 BK3_IO42 - GND (Bank 3) ...
Page 87
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name AW35 BK4_IO4 AV35 BK4_IO5 AV34 BK4_IO6 AU34 BK4_IO7 AT34 BK4_IO8 AU35 BK4_IO9 AT33 BK4_IO10 - GND (Bank 4) AU33 BK4_IO11 AW34 BK4_IO12 AV33 BK4_IO13 AR32 BK4_IO14 AT32 BK4_IO15 AU32 BK4_IO16 ...
Page 88
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name - GND (Bank 4) AW26 BK4_IO43 AV25 BK4_IO44 AT24 BK4_IO45 AU24 BK4_IO46 AU25 BK4_IO47 AW25 BK4_IO48 AW24 BK4_IO49 AU23 BK4_IO50 - GND (Bank 4) AT23 BK4_IO51 AV24 BK4_IO52 AW23 BK4_IO53 AV23 BK4_IO54 ...
Page 89
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name AT16 BK5_IO11 AW16 BK5_IO12 AU16 BK5_IO13 AV14 BK5_IO14 AV15 BK5_IO15 AU15 BK5_IO16 AW15 BK5_IO17 AT15 BK5_IO18 - GND (Bank 5) AR16 BK5_IO19 AW14 BK5_IO20 AW13 BK5_IO21 AR14 BK5_IO22 AT14 BK5_IO23 ...
Page 90
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name AU6 BK5_IO50 - GND (Bank 5) AV6 BK5_IO51 AR8 BK5_IO52 AT7 BK5_IO53 AU5 BK5_IO54 AV5 BK5_IO55 AW5 BK5_IO56 AW4 BK5_IO57 AT6 BK5_IO58 - GND (Bank 5) AV4 BK5_IO59 AR6 BK5_IO60 AU4 BK5_IO61 ...
Page 91
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name AK2 BK6_IO23 AK1 BK6_IO24 AJ4 BK6_IO25 AJ3 BK6_IO26 - GND (Bank 6) AH4 BK6_IO27 AH3 BK6_IO28 AH2 BK6_IO29 AH1 BK6_IO30 AG4 BK6_IO31 AF5 BK6_IO32 AG3 BK6_IO33 AG2 BK6_IO34 - GND (Bank 6) ...
Page 92
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name Y5 BK6_IO61 - GND (Bank 6) - GND (Bank 7) W3 BK7_IO0 W1 BK7_IO1 W2 BK7_IO2 - GND (Bank 7) W4 BK7_IO3 V1 BK7_IO4 V2 BK7_IO5 V3 BK7_IO6 V4 BK7_IO7 W5 BK7_IO8 U1 BK7_IO9 U2 BK7_IO10 - GND (Bank 7) U3 BK7_IO11 U4 BK7_IO12 T1 BK7_IO13 T2 BK7_IO14 T3 BK7_IO15 ...
Page 93
... Lattice Semiconductor ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) 680-Ball fpBGA Signal Name L3 BK7_IO35 J1 BK7_IO36 J2 BK7_IO37 M4 BK7_IO38 H1 BK7_IO39 J3 BK7_IO40 L4 BK7_IO41 M5 BK7_IO42 - GND (Bank 7) H2 BK7_IO43 K4 BK7_IO44 G1 BK7_IO45 H3 BK7_IO46 J4 BK7_IO47 K5 BK7_IO48 G3 BK7_IO49 H4 BK7_IO50 - GND (Bank 7) F2 BK7_IO51 G2 BK7_IO52 H5 BK7_IO53 F3 BK7_IO54 F1 BK7_IO55 G4 BK7_IO56 ...
Page 94
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA 900 fpBGA Ball Signal Name D3 BK0_IO0 E3 BK0_IO1 C2 BK0_IO2 - GND (Bank 0) C1 BK0_IO3 E4 BK0_IO4 F5 BK0_IO5 D2 BK0_IO6 - - D1 BK0_IO7 F4 BK0_IO8 F3 BK0_IO9 E2 BK0_IO10 - GND (Bank 0) E1 BK0_IO11 G6 BK0_IO12 G5 BK0_IO13 F1 BK0_IO14 F2 BK0_IO15 G4 BK0_IO16 G3 BK0_IO17 G2 BK0_IO18 - GND (Bank 0) G1 ...
Page 95
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name L2 BK0_IO35 L6 BK0_IO36 L5 BK0_IO37 M1 BK0_IO38 - - M2 BK0_IO39 L3 BK0_IO40 L4 BK0_IO41 M6 BK0_IO42 - GND (Bank 0) M5 BK0_IO43 M4 BK0_IO44 M3 BK0_IO45 N1 BK0_IO46 - - N2 BK0_IO47 N7 BK0_IO48 N6 BK0_IO49 P1 BK0_IO50 - GND (Bank 0) P2 BK0_IO51 N3 BK0_IO52 N4 BK0_IO53 P6 BK0_IO54 P5 BK0_IO55 ...
Page 96
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name - - T1 BK1_IO1 U2 BK1_IO2 - GND (Bank 1) U1 BK1_IO3 U3 BK1_IO4 U4 BK1_IO5 V1 BK1_IO6 V2 BK1_IO7 U5 BK1_IO8 U6 BK1_IO9 V4 BK1_IO10 - GND (Bank 1) V3 BK1_IO11 V6 BK1_IO12 V7 BK1_IO13 W1 BK1_IO14 W2 BK1_IO15 W3 BK1_IO16 - - W4 BK1_IO17 W5 BK1_IO18 - GND (Bank 1) W6 ...
Page 97
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AB1 BK1_IO35 AC6 BK1_IO36 AC5 BK1_IO37 AC2 BK1_IO38 AC1 BK1_IO39 AC4 BK1_IO40 AC3 BK1_IO41 AD2 BK1_IO42 - GND (Bank 1) AD1 BK1_IO43 AD3 BK1_IO44 AD4 BK1_IO45 AE2 BK1_IO46 AE1 ...
Page 98
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AK5 BK2_IO7 AE7 BK2_IO8 AF7 BK2_IO9 AG7 BK2_IO10 - GND (Bank 2) AH7 BK2_IO11 AE8 BK2_IO12 AF8 BK2_IO13 AJ6 BK2_IO14 AK6 BK2_IO15 AG8 BK2_IO16 AH8 BK2_IO17 AJ7 BK2_IO18 - GND (Bank 2) ...
Page 99
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AJ12 BK2_IO43 AD13 BK2_IO44 AE13 BK2_IO45 AK13 BK2_IO46 - - AJ13 BK2_IO47 AG13 BK2_IO48 AH13 BK2_IO49 AE14 BK2_IO50 - GND (Bank 2) AF14 BK2_IO51 AG14 BK2_IO52 AH14 BK2_IO53 AJ14 BK2_IO54 - - AK14 ...
Page 100
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AJ18 BK3_IO14 - - AK18 BK3_IO15 AE18 BK3_IO16 AD18 BK3_IO17 AJ19 BK3_IO18 - GND (Bank 3) AK19 BK3_IO19 AH19 BK3_IO20 AG19 BK3_IO21 AK20 BK3_IO22 AJ20 BK3_IO23 AF19 BK3_IO24 AE19 BK3_IO25 AH20 ...
Page 101
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AJ25 BK3_IO50 - GND (Bank 3) AK25 BK3_IO51 AF24 BK3_IO52 AE24 BK3_IO53 AK26 BK3_IO54 AJ26 BK3_IO55 AH25 BK3_IO56 AG25 BK3_IO57 AK27 BK3_IO58 - GND (Bank 3) AJ27 BK3_IO59 AG26 BK3_IO60 AH26 ...
Page 102
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name AC27 BK4_IO21 AD29 BK4_IO22 AD30 BK4_IO23 AB24 BK4_IO24 AB25 BK4_IO25 AC29 BK4_IO26 - GND (Bank 4) AC30 BK4_IO27 AB27 BK4_IO28 AB26 BK4_IO29 AB30 BK4_IO30 - - AB29 BK4_IO31 AA26 BK4_IO32 AA27 ...
Page 103
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name U27 BK4_IO57 U29 BK4_IO58 - GND (Bank 4) U30 BK4_IO59 T30 BK4_IO60 - - T29 BK4_IO61 - GND (Bank 4) T28 GCLK4 T27 GCLK5 T26 VCCP1 R28 GNDP1 R27 GCLK6 R26 GCLK7 - GND (Bank 5) ...
Page 104
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name K30 BK5_IO22 - - K29 BK5_IO23 L28 BK5_IO24 L27 BK5_IO25 L26 BK5_IO26 - GND (Bank 5) L25 BK5_IO27 K27 BK5_IO28 K26 BK5_IO29 J30 BK5_IO30 - - J29 BK5_IO31 J26 BK5_IO32 J27 BK5_IO33 H30 ...
Page 105
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name G25 BK5_IO57 F26 BK5_IO58 - GND (Bank 5) E28 BK5_IO59 E27 BK5_IO60 D28 BK5_IO61 C27 CFG0 B28 DONE A28 PROGRAMb D26 BK6_IO0 C26 BK6_IO1 B27 BK6_IO2 - GND (Bank 6) A27 ...
Page 106
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name D21 BK6_IO29 A21 BK6_IO30 B21 BK6_IO31 F20 BK6_IO32 - - E20 BK6_IO33 D20 BK6_IO34 - GND (Bank 6) C20 BK6_IO35 F19 BK6_IO36 E19 BK6_IO37 B20 BK6_IO38 A20 BK6_IO39 D19 BK6_IO40 C19 ...
Page 107
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name B15 BK7_IO1 C15 BK7_IO2 - GND (Bank 7) D15 BK7_IO3 E15 BK7_IO4 F15 BK7_IO5 A14 BK7_IO6 - - B14 BK7_IO7 C14 BK7_IO8 D14 BK7_IO9 E14 BK7_IO10 - GND (Bank 7) F14 BK7_IO11 C13 ...
Page 108
... Lattice Semiconductor ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) 900 fpBGA Ball Signal Name F10 BK7_IO36 G10 BK7_IO37 A8 BK7_IO38 B8 BK7_IO39 D9 BK7_IO40 - - E9 BK7_IO41 A7 BK7_IO42 - GND (Bank 7) B7 BK7_IO43 C8 BK7_IO44 D8 BK7_IO45 A6 BK7_IO46 B6 BK7_IO47 E8 BK7_IO48 F8 BK7_IO49 C7 BK7_IO50 - GND (Bank 7) D7 BK7_IO51 E7 BK7_IO52 F7 BK7_IO53 A5 BK7_IO54 ...
Page 109
... Lattice Semiconductor Part Number Description LFX XXXX X X – XX XXXXX X Device Family LFX Gates 125 = 139K Gates 200 = 210K Gates 500 = 476K Gates 1200 = 1.25M Gates sysHSI Support Blank = Supports sysHSI sysHSI Support Power Supply Voltage B = 2.5/3. 1.8V 1. Select products only. See Ordering Information tables below for specific support. ...
Page 110
... Lattice Semiconductor Part Number Gates LFX200B-05F516C 210K LFX200B-04F516C 210K LFX200B-03F516C 210K LFX200C-04F516C 210K LFX200C-03F516C 210K 1 LFX200B-05FH516C 210K 1 LFX200B-04FH516C 210K 1 LFX200B-03FH516C 210K 1 LFX200C-04FH516C 210K 1 LFX200C-03FH516C 210K LFX500B-05F516C 476K LFX500B-04F516C 476K LFX500B-03F516C 476K LFX500C-04F516C 476K LFX500C-03F516C 476K 1 LFX500B-05FH516C 476K 1 LFX500B-04FH516C 476K 1 LFX500B-03FH516C 476K ...
Page 111
... Part Number Gates LFX125EB-05F256C 139K LFX125EB-04F256C 139K LFX125EB-03F256C 139K LFX125EC-04F256C 139K LFX125EC-03F256C 139K LFX125EB-05F516C 139K LFX125EB-04F516C 139K LFX125EB-03F516C 139K LFX125EC-04F516C 139K LFX125EC-03F516C 139K 1 LFX125EB-05FH516C 139K 1 LFX125EB-04FH516C 139K 1 LFX125EB-03FH516C 139K 1 LFX125EC-04FH516C 139K 1 LFX125EC-03FH516C 139K LFX200EB-05F256C 210K LFX200EB-04F256C 210K LFX200EB-03F256C 210K LFX200EC-04F256C 210K LFX200EC-03F256C ...
Page 112
... LFX1200EC-04F900C 1.25M LFX1200EC-03F900C 1.25M LFX1200EB-05FE680C 1.25M LFX1200EB-04FE680C 1.25M LFX1200EB-03FE680C 1.25M LFX1200EC-04FE680C 1.25M LFX1200EC-03FE680C 1.25M 1. FH516 package was converted to F516 via PCN# 09A-08. Part Number Gates LFX125EB-04F256I 139K LFX125EB-03F256I 139K LFX125EC-03F256I 139K LFX125EB-04F516I 139K LFX125EB-03F516I 139K LFX125EC-03F516I 139K 1 LFX125EB-04FH516I 139K 1 LFX125EB-03FH516I 139K ...
Page 113
... LFX200C-04FN256C 210K LFX200C-03FN256C 210K LFX500B-05FN900C 476K LFX500B-04FN900C 476K LFX500B-03FN900C 476K LFX500C-04FN900C 476K LFX500C-03FN900C 476K Part Number Gates LFX125EB-05FN256C 139K LFX125EB-04FN256C 139K LFX125EB-03FN256C 139K LFX125EC-04FN256C 139K LFX125EC-03FN256C 139K LFX200EB-05FN256C 210K LFX200EB-04FN256C 210K LFX200EB-03FN256C 210K LFX200EC-04FN256C 210K LFX200EC-03FN256C 210K LFX500EB-05FN900C 476K LFX500EB-04FN900C 476K ...
Page 114
... Lattice Semiconductor Part Number Gates LFX125EB-04FN256I 139K LFX125EB-03FN256I 139K LFX125EC-03FN256I 139K LFX200EB-04FN256I 210K LFX200EB-03FN256I 210K LFX200EC-03FN256I 210K LFX500EB-04FN900I 476K LFX500EB-03FN900I 476K LFX500EC-03FN900I 476K For Further Information In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispXPGA Family: • ...
Page 115
... Lattice Semiconductor Revision History (Cont.) Date Version July 2004 09.0 Added “E” Series product family. August 2004 10.0 Final release. December 2004 10.1 Updated NC Connections table. April 2005 10.2 Clarification of IDK specification. April 2005 11.0 Select lead-free packages release. ...