LFE2M70E-7FN900C | |
|---|---|
| Manufacturer Part Number | LFE2M70E-7FN900C |
| Description | IC FPGA 50KLUTS 410I/O 900-BGA |
| Manufacturer | Lattice |
| LFE2M70E-7FN900C datasheets |
|
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Specifications of LFE2M70E-7FN900C | |||
|---|---|---|---|
| Lead Free Status / Rohs Status | Lead free / RoHS Compliant | Other names | 220-1220 |
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PrevNext
Lattice Semiconductor
Table 2-6. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode
is supported for all data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-20.
Memory Mode
Configurations
16,384 x 1
8,192 x 2
4,096 x 4
Single Port
2,048 x 9
1,024 x 18
512 x 36
16,384 x 1
8,192 x 2
True Dual Port
4,096 x 4
2,048 x 9
1,024 x 18
16,384 x 1
8,192 x 2
4,096 x 4
Pseudo Dual Port
2,048 x 9
1,024 x 18
512 x 36
2-19
Architecture
LatticeECP2/M Family Data Sheet
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Lattice Semiconductor Corp. |
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 LFE2M70E-5FN900C |
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900 | LATTICE SEMICONDUCTOR |
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 LFE2M70E-6FN900I |
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LFE2M70E-5FN1152C |
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LFE2M70E-5FN900I |
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|
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LFE2M70E-6FN1152C |
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LFE2M70E-5FN1152I |
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LFE2M70E-7FN1152C |
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LFE2M70E-6FN1152I |
IC FPGA 67KLUTS 1152FPBGA | Lattice | |
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LFE2M70SE-5FN900C |
IC FPGA 67KLUTS 900FPBGA | Lattice |
|
|
LFE2M70SE-5FN1152C |
IC FPGA 67KLUTS 1152FPBGA | Lattice | |
|
LFE2M70SE-6FN900C |
IC FPGA 67KLUTS 900FPBGA | Lattice |
|
|
LFE2M70SE-5FN900I |
IC FPGA 67KLUTS 900FPBGA | Lattice |
|
|
LFE2M70SE-6FN1152C |
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|
