SLXT973QE.A2 Intel, SLXT973QE.A2 Datasheet - Page 30

SLXT973QE.A2

Manufacturer Part Number
SLXT973QE.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QE.A2

Lead Free Status / Rohs Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.5.3.1
3.5.3.2
3.5.4
30
The lowest power operation is achieved using the global power-down pin. This active High pin
powers down every circuit in the device, including all clocks. All registers are unaltered and
maintained when the global PWRDWN pin is released and the registers are reloaded with the value
of the last hardware reset.
Individual ports (software power-down) can be powered down using Control Register bit 0.11.
This bit powers down a significant portion of the port, but clocks to the register section remain
active. This allows the management interface to remain active during register power-down. The
power-down bit is active High.
Hardware Power-Down
The hardware power-down per port mode is controlled by the PWRDWN 0/1 pins. When
PWRDWN 0/1 is High, the following conditions are true:
Software Power-Down
Software port power-down control is provided by Register 11 in the respective port Control
Registers (refer to
conditions are true:
Reset
The LXT973 provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, settings for Register bits 0.13, 0.12, and 0.8 are read in from the pins (refer to
page 31
During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins, and
revert back to the values that were read in during the last hardware reset. Any changes to pin values
from the last hardware reset are not detected during a software reset. Also, during a software reset
(Register bit 0.15 = 1), the registers are available for reading. The reset bit is polled to see when the
part has completed reset (Register bit 0.15 = 0).
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
All the MII interface pins are disabled during a hardware reset and released to the bus on de-
assertion of reset.
All LXT973 ports and the clock are shut down.
All outputs are tri-stated.
The MDIO registers are not accessible.
Configuration pins are not read upon release of the PWRDWN 0/1 pins, and registers are
reloaded with the value of the last hardware reset.
The individual port is shut down.
The MDIO registers remain accessible.
The register remains unchanged.
for pin settings and
Table 17 on page
Table 17 on page 62
62). During individual port power-down, the following
for register bit definitions).
Rev. Date: March 1, 2002
Document #: 249426
Table 9 on
Revision #: 002
Datasheet

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