SLXT973QE.A2 Intel, SLXT973QE.A2 Datasheet - Page 49

SLXT973QE.A2

Manufacturer Part Number
SLXT973QE.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QE.A2

Lead Free Status / Rohs Status
Not Compliant
5.0
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 13. Configuration Settings (Hardware Control Interface)
When the LXT973 is first powered on, reset, or encounters a link-down state, it must determine the
line speed and operating conditions to use for the network link. The LXT973 first checks the
MDIO registers (initialized via the Hardware Control Interface or written by software) for
operating instructions. Using these mechanisms, the user can command the LXT973 to do one of
the following:
In forced twisted-pair link operation, the LXT973 immediately begins operating the network
interface as commanded. In the last case, the LXT973 begins the auto-negotiation/parallel-
detection process.
Several pins are used to configure the LXT973 device.
configurations to the port. Usually these pins are decodes of chip pins. This is useful for manual
configuration.
Configuration
FIBER_TPn
1. These pins also set the default values for Registers 0 and 4 accordingly.
Forced 100BASE-FX operation
Forced twisted-pair link operation to:
Allow auto-negotiation/parallel-detection.
High
High
High
High
High
Low
Low
— 100BASE-TX, full-duplex
— 100BASE-TX, half-duplex
— 10BASE-T, full-duplex
— 10BASE-T, half-duplex
AUTO_NEGx
High
High
High
High
Low
-
-
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
SPEEDx
High
High
High
Low
Low
-
-
DUPLEXx
High
High
High
High
Low
Low
Low
100BASE-FX is enabled in half-duplex mode.
Auto-negotiation is disabled
100BASE-FX is enabled in full-duplex mode.
Auto-negotiation is disabled.
AUTO_NEG is enabled. All capabilities are
advertised.
Register bits 4.8, 4.7, 4.6 and 4.5 are all set to 1.
AUTO_NEG is enabled. Only 100 Mbps
capabilities are advertised.
Register bits 4.8 and 4.7are set to 1. Register bits
4.6 and 4.5 are cleared to 0.
AUTO_NEG is enabled. Only 10 Mbps capabilities
are advertised.
Register bits 4.8 and 4.7 are cleared to 0. Register
bits 4.6 and 4.5 are set to 1.
AUTO_NEG is enabled. Only half-duplex
capabilities are advertised.
Register bits 4.7 and 4.5 are set 1. Register bits
4.8 and 4.6 are cleared to 0.
AUTO_NEG is disabled. LXT973 port x is forced
to 100 Mbps full-duplex operation.
Table 13
summarizes the available manual
Mode
49

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