SLXT973QE.A2 Intel, SLXT973QE.A2 Datasheet - Page 78

• Manufacturer Part Number: SLXT973QE.A2
• Manufacturer: Intel

Specifications of SLXT973QE.A2

• Lead Free Status / Rohs Status: Not Compliant

LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
78
Figure 28. 100BASE-TX Receive Timing - 4B Mode
Table 41. MII - 100BASE-TX Receive Timing Parameters - 4B Mode
RXD<3:0>, RXDV, RXER setup to
RXCLK High
RXD<3:0>, RXDV, RXER hold
from RXCLK High
CRS asserted to RXD<3:0>, RXDV
Receive start of
“J” to CRS asserted
Receive start of “T” to CRS de-
asserted
Receive start of “J” to COL
asserted
Receive start of “T” to COL de-
asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
Parameter
NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and
Twisted-Pair
RXD<3:0>
RXCLK
DPAP/N_1.
RXDV
Input
CRS
COL
0ns
Sym
t1
t2
t3
t4
t5
t6
t7
t4
t6
Min
10
10
10
10
14
11
3
Typ
t3
14
17
–
–
4
–
–
1
250ns
Max
16
17
15
20
–
–
5
t5
t7
t1
t2
Units
BT
BT
BT
BT
BT
ns
ns
Rev. Date: March 1, 2002
Document #: 249426
Conditions
Revision #: 002
Datasheet
Test
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