M28W320FCT70N6E Micron Technology Inc, M28W320FCT70N6E Datasheet
M28W320FCT70N6E
Specifications of M28W320FCT70N6E
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M28W320FCT70N6E Summary of contents
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... Electronic Signature – Manufacturer Code: 20h – Top Device Code, M28W320FCT: 88BAh – Bottom Device Code, M28W320FCB: 88BBh RoHS compliant packages November 2008 M28W320FCT M28W320FCB 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory FBGA TFBGA47 (ZB) 6.39 x 6.37mm TSOP48 ( 20mm 208010-05 1/69 1 www.numonyx.com ...
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Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Erase Status (Bit 6.4 Program Status (Bit 6.5 V Status (Bit 6.6 Program Suspend Status (Bit 6.7 Block Protection Status (Bit 6.8 Reserved (Bit Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Appendix B Common Flash Interface (CFI 3/69 ...
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Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Appendix D Command interface ...
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List of tables Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic Diagram ...
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... Summary description The M28W320FCT and M28W320FCB are 32 Mbit (2 Mbit x 16) non-volatile Flash memories that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. V DDQ supply is provided to speed up customer programming. ...
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Figure 1. Logic Diagram Table 1. Signal Names A0-A20 DQ0-DQ15 DDQ 8/ DDQ A0-A20 W E M28W320FCT M28W320FCB G RP ...
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Figure 2. TSOP Connections A15 A14 A13 A12 A11 A10 A20 A19 A18 A17 A16 V DDQ V SS DQ15 DQ7 DQ14 DQ6 DQ13 ...
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Figure 3. TFBGA Connections (Top view through package A13 A11 B A14 A10 C A15 A12 D A16 DQ14 E V DDQ DQ15 DQ7 10/ A18 ...
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Figure 4. Block Addresses M28W320FCT Top Boot Block Addresses 1FFFFF 4 KWords 1FF000 1F8FFF 4 KWords 1F8000 1F7FFF 32 KWords 1F0000 00FFFF 32 KWords 008000 007FFF 32 KWords 000000 1. Also see and Appendix A, Table 24 Figure 5. Protection ...
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Signal descriptions See Figure 1: Logic Diagram connected to this device. 2.1 Address inputs (A0-A20) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands ...
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Reset (RP) The Reset input provides a hardware reset of the memory. When Reset memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in ...
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... Read Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must should be used to enable the device. Output Enable should be used to gate data onto the output ...
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Automatic Standby Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V will still output data if ...
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Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the ...
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... FFh 4.4 Read CFI Query command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area ...
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Block Erase command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then ...
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Double Word Program command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when V Three ...
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Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will ...
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Block Lock command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required ...
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Table 4. Commands Commands 1st Cycle Op Add Read Memory 1+ Write X Array Read Status 1+ Write X Register Read Electronic 1+ Write X Signature Read CFI Query 1+ Write X Erase 2 Write X Program 2 Write ...
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Table 5. Read Electronic Signature Code Device Manufacture. V Code M28W320FCT V Device Code M28W320FCB Table 6. Read Block Lock Signature Block Status Locked Block ...
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Table 8. Program, Erase Times and Program/Erase Endurance Cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) Data Retention 1. Typical time to ...
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Block locking The M28W320FCT and M28W320FCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows ...
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Lock-Down state Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing ...
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Table 10. Protection Status (1) Current Protection Status (WP, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) 1,0,1 no 1,1,0 yes 1,1,1 no 0,0,0 yes (2) 0,0,1 no 0,1 The lock status is defined by the write ...
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Status Register The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, ...
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Erase Status (Bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller ...
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Block Protection Status (Bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High ...
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Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow are derived from tests performed under the ...
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Figure 7. AC Measurement Load Circuit V DDQ 0.1µF (1) Table 14. Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI ...
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Table 15. DC Characteristics (continued) Symbol Parameter Program Current I PP1 (Read or Stand-by) I Program Current (Reset) PP2 I Program Current (Program) PP3 I Program Current (Erase) PP4 V Input Low Voltage IL V Input High Voltage IH V ...
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Figure 8. Read AC Waveforms A0-A20 E G DQ0-DQ15 ADDR. VALID CHIP ENABLE Table 16. Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC (1) ...
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Figure 9. Write AC Waveforms, Write Enable Controlled 36/69 ...
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Table 17. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Write Enable High AVWH Data Valid to Write Enable High DVWH Chip ...
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Figure 10. Write AC Waveforms, Chip Enable Controlled 38/69 ...
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Table 18. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Chip Enable High AVEH Data Valid to Chip Enable High DVEH DS Chip Enable High ...
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Figure 11. Power-Up and Reset AC Waveforms tVDHPH VDD, VDDQ Power-Up Table 19. Power-Up and Reset AC Characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, Chip t PHEL Enable Low, Output Enable Low ...
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Package mechanical Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline 1 N/2 TSOP-a 1. Drawing is not to scale. Table 20. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, ...
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Figure 13. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" Drawing is not to scale. Table 21. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical ...
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Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package ...
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Part numbering Table 22. Ordering Information Scheme Example: Device Type M28 Operating Voltage 2.7V to 3.6V Device Function 320FC = 32 Mbit (2 Mb x16), Boot Block Array Matrix T = Top Boot ...
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Table 23. Daisy Chain Ordering Scheme Example:M28W320FC Device Type M28W320FC Daisy Chain -ZB = TFBGA47: 6.39 x 6.37mm, 0.75 mm pitch Option E = RoHS compliant Package, Standard Packing F = RoHS compliant Package, Tape & Reel 24mm Packing Devices ...
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Appendix A Block address tables Table 24. Top Boot Block Addresses, M28W320FCT # ...
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Table 24. Top Boot Block Addresses, M28W320FCT (continued ...
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Table 24. Top Boot Block Addresses, M28W320FCT (continued Table 25. Bottom Boot Block Addresses, M28W320FCB # ...
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Table 25. Bottom Boot Block Addresses, M28W320FCB (continued ...
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Table 25. Bottom Boot Block Addresses, M28W320FCB (continued 50/69 Size (KWord) Address Range 4 007000-007FFF 4 006000-006FFF 4 005000-005FFF 4 004000-004FFF 4 003000-003FFF 4 002000-002FFF 4 001000-001FFF 4 000000h - 000FFFh ...
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... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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Table 27. CFI Query Identification String Offset Data 17h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (0000h means none exists) 18h 0000h 19h 0000h Address for Alternate Algorithm extended Query table ...
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... Table 29. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number of Erase Block Regions within the device. 2Ch 0002h It specifies the number of regions within the device containing contiguous Erase Blocks of the same size ...
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Table 30. Primary Algorithm-Specific Extended Query Table Offset Data ( 35h (P+0)h = 35h 0050h (P+1)h = 36h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” (P+2)h = 37h 0049h (P+3)h = 38h 0031h Major version ...
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Table 30. Primary Algorithm-Specific Extended Query Table Offset Data ( 35h (P+F)h = 44h 0080h Protection Field 1: Protection Description This field describes user-available. One Time Programmable (OTP) (P+10)h = 45h 0000h Protection register bytes. Some are pre-programmed ...
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... Status check of b1 (Protected Block after a sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. 56/69 program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10 writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address) ; ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7== 0) ...
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... Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1. 58/69 quadruple_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; writeToFlash (addressToProgram3, dataToProgram3) ; writeToFlash (addressToProgram4, dataToProgram4) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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... Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ Write FFh } } ...
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... YES YES End error is found, the Status Register must be cleared before further Program/Erase operations. 60/69 erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... Erase Complete { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (any_address, 0xFF) ; read_program_data ( ); Write FFh /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase ...
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... Read Block Signature table )*/ writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ } AI04364 ...
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... YES End 1. Status check of b1 (Protected Block after a sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address) ; ...
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Appendix D Command interface and Program/Erase Controller state Table 32. Write State Machine Current/Next, sheet Data Current State When Read bit Read Array 7 (FFh) Read Read Array “1” Array Array Read Read Status “1” Status ...
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Table 32. Write State Machine Current/Next, sheet Data Current State When Read bit Read Array 7 (FFh) Erase Setup “1” Status Erase Read “1” Status Cmd.Error Array Erase “0” Status (continue) Erase Sus Erase Sus “1” ...
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Table 33. Write State Machine Current/Next, sheet Read Read CFI Current State Elect.Sg. Query (90h) Read Read CFI Read Array Elect.Sg. Query Read Read CFI Read Status Elect.Sg. Query Read Read CFI Read Elect.Sg. Elect.Sg. Query Read ...
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Table 33. Write State Machine Current/Next, sheet (continued) Read Read CFI Current State Elect.Sg. Query (90h) Erase (continue) Erase Erase Erase Suspend Suspend Suspend Read Read CFI Read Ststus Elect.Sg. Query Erase Erase Erase Suspend Suspend Read ...
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Revision history Table 34. Document revision history Date Revision 24-May-2004 23-Aug-2004 12-Jul-2005 28-Mar-2006 16-Oct-2006 10-Dec-2007 18-Nov-2008 68/69 0.1 First Issue Figure 2: TSOP Connections 0.2 (Top view through package). Datasheet status promoted to Full Datasheet. 85, 90 and 100ns ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...