M25P128-VME6GB Micron Technology Inc, M25P128-VME6GB Datasheet
M25P128-VME6GB
Specifications of M25P128-VME6GB
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M25P128-VME6GB Summary of contents
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... JEDEC standard two-byte signature (2018h) More than 10,000 erase/program cycles per sector More than 20-year data retention RoHS compliant packages March 2010 128-Mbit, low-voltage, serial flash memory with 54-MHz SPI bus interface = 9 V) for Rev 6 M25P128 VDFPN8 (ME (MLP8) SO16 (MF) 300 mils width 1/47 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M25P128 is a 128-Mbit (16 Mbit × 8) serial flash memory, with advanced write protection mechanisms and accessed by a high speed SPI-compatible bus, which allows clock frequency operation MHz The memory can be programmed 1 to 256 Bytes at a time, using the page program instruction ...
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... PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. Figure 3. SO connections Don’t use 2. See Package mechanical section for package dimensions, and how to identify pin-1. Description M25P128 HOLD W M25P128 HOLD ...
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Signal description 2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial data input (D) This input ...
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Write protect/enhanced program supply voltage (W/V W/V is both a control input and a power supply pin. The two functions are selected by the PP voltage range applied to the pin. If the W/V input is kept in a ...
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SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge ...
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Figure 5. SPI modes supported CPOL CPHA MSB Q MSB AI01438B 11/47 ...
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Operating features 4.1 Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
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Table 2. Protected area sizes Status Register content BP2 Bit BP1 Bit BP0 Bit The device is ready to accept a Bulk Erase ...
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Figure 6. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 15/47 ...
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Memory organization The memory is organized as: 16777216 bytes (8 bits each) 64 sectors (2 Mbits, 262144 bytes each) 65536 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device ...
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Table 3. Memory organization Sector ...
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Table 3. Memory organization (continued) Sector 18/47 Address Range 700000h 6C0000h ...
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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven ...
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Write enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) ...
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Read identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device ...
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Read status register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. ...
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Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read status register (RDSR) instruction sequence and data-out sequence Instruction D High Impedance Q ...
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Write status register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/V When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to ...
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Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising ...
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Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) ...
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Page program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the ...
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Figure 15. Page program (PP) instruction sequence Instruction Data Byte ...
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Sector erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Power-up and power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 18. Power-up timing (max) Program, Erase and Write Commands are Rejected by the Device V CC (min) Reset State of the Device V WI Table 8. Power-up timing and V Symbol ( (min) ...
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Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 14. DC characteristics for 65 nm devices Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Operating Current (READ) CC3 I Operating Current (PP) CC4 Operating Current I CC5 (WRSR) I ...
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Table 15. AC characteristics for 65 nm devices Test conditions specified in Symbol Alt Data In Setup Time DVCH DSU t t Data In Hold Time CHDX Active Hold Time (relative to C) CHSH t ...
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When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If only a single byte is programmed, the estimated ...
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Table 17. AC characteristics for 130 nm devices Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, WREN, WRDI RDID, RDSR, WRSR f Clock frequency for READ instructions R ...
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Table 17. AC characteristics for 130 nm devices (continued) Symbol Alt and t must be greater than or equal to 1 Value is guaranteed by characterization, not 100% tested in production. 3. Expressed ...
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Figure 21. Write protect setup and hold timing during WRSR when SRWD =1 W/V PP tWHSL High Impedance Q Figure 22. Hold timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439b tHHCH AI02032 ...
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Figure 23. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 24. V timing PPH PPH W/V PP tVPPHSL 42/47 tCH tCLQV tQLQH tQHQL End of PP (identified by WPI ...
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Package mechanical Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position ...
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Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width B SO-H 1. Drawing is not to scale. Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width Symbol Typ A A1 ...
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... Numonyx sales office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M25P128 – ...
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Revision history Table 21. Document revision history Date Revision 02-May-2005 09-Jun-2005 28-Aug-2005 20-Jan-2006 17-Oct-2006 10-Dec-2007 26-Nov-2009 17-Dec-2009 1-Feb-2010 46/47 0.1 First issue. Table 2: Protected area sizes 0.2 Memory capacity modified in Updated t values in Table 17: AC ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...