M29W128GL70N6E Micron Technology Inc, M29W128GL70N6E Datasheet
M29W128GL70N6E
Specifications of M29W128GL70N6E
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M29W128GL70N6E Summary of contents
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... Minimum 100,000 program/erase cycles per block RoHS compliant packages Automotive device grade: Temperature -40 °C to 125 °C (Automotive grade certified) /WP PP /WP PP Rev 10 M29W128GH M29W128GL 3 V supply flash memory BGA BGA TBGA64 (ZA) FBGA (ZS Device code 227Eh + 2221h + 2201h 227Eh + 2221h + 2200h www.numonyx.com 1/94 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix A Block addresses and read/modify protection groups . . . . . . . . . . 79 Appendix B Common flash interface (CFI Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 C.1 Factory locked extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . 88 C.2 Customer lockable extended memory block . . . . . . . . . . . . . . . . . . . . . . . 89 Appendix D Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4/94 ...
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M29W128GH and M29W128GL are 128-Mbit (8 Mbit x16 or 16 Mbit x8) non-volatile flash memories that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its read mode. The memory array is divided into 64-Kword/128-Kbyte uniform blocks that can be erased independently possible to preserve valid data while old data is erased ...
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Table 2. Signal names Name A0-A22 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A 1 Data input/output or address input E Chip enable G Output enable W Write enable RP Reset RB Ready/busy output BYTE Byte/word organization select V ...
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Figure 2. TSOP connections V PP /WP 10/ A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W128GH 15 42 A21 M29W128GL RB A18 A17 ...
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Figure 3. TBGA and FBGA connections (top view through package CCQ ...
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Figure 4. Block addresses (x8) Address lines A22-A0, DQ15A-1 FFFFFFh 128 Kbytes 03FFFFh 128 Kbytes 020000h 01FFFFh 128 Kbytes 000000h 12/94 (x16) Address lines A22-A0 7FFFFFh 64 Kwords 64 Kwords 00FFFFh 64 Kwords 000000h Total of 128 uniform blocks AI13332 ...
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Signal descriptions See Figure 1: Logic connected to this device. 2.1 Address inputs (A0-A22) The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent ...
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Write enable (W) The write enable pin, W, controls the bus write operation of the memory’s command interface. 2.8 V /write protect (V PP The V /write protect pin provides two functions. The V PP use an external high ...
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Reset (RP) The reset pin can be used to apply a hardware reset to the memory. A hardware reset is achieved by holding reset Low, V High the memory will be ready for bus read and bus ...
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V ground the reference for all voltage measurements. The device features two V SS which must be connected to the system ground. 16/94 pins both of SS ...
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Bus operations There are five standard bus operations that control the device. These are bus read (random and page modes), bus write, output disable, standby and automatic standby. See Table 4: Bus operations, 8-bit mode summary. Typical glitches of ...
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Reset During reset mode the memory is deselected and the outputs are high impedance. The memory is in reset mode when standby level, independently from the chip enable, output enable or write enable inputs. 3.6 ...
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These codes can also be accessed by issuing an Auto Select command (see Auto Select command). 3.7.2 Verify extended memory block protection indicator The extended memory block is either factory locked or ...
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M Table 4. Bus operations, 8-bit mode (1) Operation E G Bus read Bus write Standby Output disable Reset ...
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Table 6. Read electronic signature - auto select mode - programmer method (8-bit mode) Read (1) cycle A22-A10 A9 Manufacture r code Device code (cycle Device code (cycle 2) ...
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Table 8. Block protection - auto select mode - programmer method (8-bit mode) (1) Operation E G Verify M29W128GL extended memory block protection M29W128GH indicator (bit DQ7) Verify block protection status ...
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Hardware protection The M29W128GH and M29W128GL feature a V lowest block. Refer to 5 Software protection The M29W128GH and M29W128GL have three different software protection modes: Volatile protection Non-volatile protection Password protection On first use all parts default to ...
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Volatile protection mode The volatile protection allows the software application to easily protect blocks against inadvertent change. However, the protection can be easily disabled when changes are needed. Volatile protection bits, VPBs, are volatile and unique for each block ...
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Refer to Table 19: Block protection status details on the block protection mechanism, and to volatile protection mode command set. 5.2.2 Non-volatile protection bit lock bit The non-volatile protection bit lock bit (NVPB lock bit global volatile bit ...
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Figure 5. Software protection scheme Parameter block or main block Volatile protection Non-volatile protection 1. NVPBs default to ‘1’ (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its NVPB is set to ‘0’ and ...
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Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. Failure to observe a valid sequence of bus write operations will result in the ...
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... CFI query mode, bus read operations to the memory will output data from the common flash interface (CFI) memory area. One bus write cycle is required to issue the Read CFI Query command. This command is valid only when the device is in the read array or auto select mode ...
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Each additional block must therefore be selected within the timeout period of the last block. The timeout timer restarts when an additional block is selected. After the sixth bus write operation, a bus read operation outputs the status register. ...
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If the erase suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to erase again the blocks suspended. 6.1.7 Erase Resume command The Erase Resume command is ...
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Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four bus write operations, the final write operation latches the address and data in ...
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Table 10. Standard commands, 8-bit mode (1) Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (5) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume ...
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Table 11. Standard commands, 16-bit mode (1) Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (5) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume ...
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Fast program commands The M29W128GH/L offers a set of fast program commands to improve the programming throughput: Write to Buffer Program Enhanced Buffered Program (valid mode only) Unlock Bypass. See either Table 12, for a summary ...
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All the addresses used in the write to buffer program operation must lie within the same page. To program the content of the write buffer, this command must be followed by a Write to Buffer Program Confirm command ...
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It is possible to detect program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous and ...
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Write to Buffer Program Confirm command The Write to Buffer Program Confirm command is used to confirm a Write to Buffer Program command and to program the N+1 words/bytes loaded in the write buffer by this command. 6.2.5 Enhanced ...
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Unlock Bypass Block Erase command The Unlock Bypass Block Erase command can be used to erase one or more memory blocks at a time. The command requires two bus write operations instead of six using the standard Block Erase ...
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Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to read/reset mode from unlock bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit ...
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Table 13. Fast program commands, 16-bit mode 1st Command Add Write to Buffer N+5 555 Program Write to Buffer BAd 1 (5) Program Confirm Buffered Program 3 555 Abort and Reset Unlock Bypass 3 555 Unlock Bypass 2 X Program ...
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Protection commands Blocks can be protected individually against accidental program, erase or read operations. The device block protection scheme is shown in either 15, or Table summary of the block protection commands. Block protection commands are available both in ...
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Exit Extended Memory Block command The Exit Extended Memory Block command is used to exit from the extended memory block mode and return the device to read mode. Four bus write operations are required to issue the command. 6.3.3 ...
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Password Read command The Password Read command is used to verify the password used in password protection mode. To verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus ...
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Figure 6. NVPB program/erase algorithm 44/94 Enter NVPB command set. Program NVPB Addr = BAd Read Byte twice Addr = BAd NO DQ6= Toggle YES NO DQ5=1 Wait 500 μs YES Read Byte twice Addr = BAd NO DQ6= Read ...
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NVPB lock bit command set Enter NVPB Lock Bit Command Set command Three bus write cycles are required to issue the Enter NVPB Lock Bit Command Set command. Once the command has been issued, the commands allowing to set ...
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Table 15. Block protection commands, 8-bit mode Command 1st 2nd Ad Data Ad Data Enter Lock Register 3 AAA AA 555 55 Command (4) Set Lock Register DATA (5) Program Lock Register DATA 1 X (5) ...
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Ad address, Dat data, BAd any address in the block, RD read data, PWDn password byte PWAn password address ( 7), X don’t care. All values in the table are in hexadecimal. 2. ...
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Table 16. Block protection commands, 16-bit mode Command 1st Ad Enter Lock Register 3 555 (4) Command Set Lock Register Program 2 X Lock Register Read 1 X Enter Password Protection Command 3 555 (4) Set (6)(7) Password Program 2 ...
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Table 17. Program, erase times and program, erase endurance cycles Parameter Chip Erase (4) Block Erase (128 kbytes) Erase Suspend latency time Block Erase timeout Single Byte Program Byte Program Write to Buffer Program (64 bytes at-a-time) Single Word Program ...
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Registers The device feature two registers: A lock register that allows to configure the memory blocks and extended memory block protection (see A status register that provides information on the current or previous program or erase operations. 7.1 Lock ...
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Table 18. Lock register bits DQ15-3 DQ2 Password protection mode Don’t care lock bit 1. DQ0, DQ1 and DQ2 lock register bits are set to ‘1’ when shipped from the factory. Table 19. Block protection status Block (1) NVPB lock ...
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Figure 7. Lock register program flowchart Write Lock Register Exit command: Device returned Add Dont' care, Data 90h to Read mode Add Dont' care, Data 00h the programmed data (see Table 18: Lock register 2. The lock ...
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Status register The M29W128GH/L has one status register. The various bits convey information and errors on the current and previous program/erase operation. Bus read operations from any address within the memory, always read the status register during program and ...
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The error bit is output on DQ5 when the status register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting will set ...
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Table 20. Status register bits Operation (2) Program Program during erase suspend (2) Buffered program abort Program error Chip erase Block erase before timeout Block erase Erase suspend Erase error 1. Unspecified data bits should be ignored. DQ7 2. for ...
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Figure 8. Data polling flowchart 56/94 START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 at VALID ADDRESS DQ7 YES = DATA NO FAIL PASS AI07760 ...
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Figure 9. Data toggle flowchart START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE at Valid Address DQ6 NO = TOGGLE YES FAIL ...
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Maximum ratings Stressing the device above the rating listed in cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...
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Figure 11. AC measurement I/O waveform V CCQ 0 V Table 23. Power-up waiting timings Symbol ( High to Chip Enable Low VCHEL CC ( High to Chip Enable Low VCQHEL CCQ t V High to ...
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Table 24. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 25. DC characteristics Symbol Parameter (1) I Input leakage current LI I Output leakage current LO Random read I ...
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Figure 13. Random read AC waveforms (8-bit mode) A0-A22 E G DQ0-DQ14, DQ15A-1 Note: BYTE = V IL Figure 14. Random read AC waveforms (16-bit mode) A–1,A0-A22 E G DQ0-DQ7 Note: BYTE = V IH 62/94 VALID tAVQV tAXQX tGLQV ...
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Figure 15. BYTE transition AC waveforms A0-A22 A–1 BYTE DQ0-DQ7 DQ8-DQ15 tBLQZ Note: Chip Enable (E) and Output Enable ( VALID VALID tAVQV tBLQX Hi-Z IL tAXQX tBHQV DATA OUT DATA OUT Byte_Transition_AC-Waveform 63/94 ...
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Figure 16. Page read AC waveforms (16-bit mode) 64/94 ...
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Table 26. Read AC characteristics Symbol Alt. Parameter Address Valid to Next t t AVAV RC Address Valid Address Valid to Output t t AVQV ACC Valid Address Valid to Output t t AVQV1 PAGE Valid (page) Chip Enable Low ...
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Figure 17. Write enable controlled program waveforms (8-bit mode) tAVAV A0-A22/ A–1 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the ...
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Figure 18. Write enable controlled program waveforms (16-bit mode) tAVAV A0-A22 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ1', DQ15A–1 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the ...
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M Table 27. Write AC characteristics, write enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Chip Enable Low to Write Enable Low ELWL Write Enable Low to Write Enable ...
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Figure 19. Chip enable controlled program waveforms (8-bit mode) A0-A22/ A– DQ0-DQ7 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data ...
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Figure 20. Chip enable controlled program waveforms (16-bit mode) A0-A22 DQ0-DQ14 A–1 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data ...
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Figure 21. Chip/block erase waveforms (8-bit mode) tAVAV A0-A22/ A–1 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a ...
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Figure 22. Reset AC waveforms (no program/erase ongoing tPLPX Figure 23. Reset during program/erase operation AC waveforms tPLPX Table 29. Reset AC characteristics Symbol Alt. t (2) READ t RP ...
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Figure 24. Accelerated program timing waveforms V PPH tVHVPP Figure 25. Data polling AC waveforms tWHEH DQ7 DATA DQ6-DQ0 DATA R/B 1. DQ7 returns valid data bit when the ...
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Figure 26. Toggle/alternative toggle bit polling AC waveforms (8-bit mode) A0-A22/ A–1 E tWHGL2 W G tWHDX DQ6/DQ2 Data tWHRL R/B 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing ...
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Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard ...
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Figure 28. TBGA64 active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 32. TBGA64 ...
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Figure 29. FBGA64 mm— active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 33. FBGA64 mm—8 x ...
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... Device type M29 Operating voltage 2 Device function 128GH = 128-Mbit (x8/x16), page, uniform block, flash memory, highest block protected by V 128GL = 128-Mbit (x8/x16), page, uniform block, flash memory, lowest block protected by V Speed ( ( ( (available only with option 6) Package N = TSOP56 TBGA64 mm pitch ...
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Appendix A Block addresses and read/modify protection groups Table 35. Block addresses Block Protection group 0 Protection group 1 Protection group 2 Protection group 3 Protection group 4 Protection group 5 Protection group 6 Protection group 7 Protection group 8 ...
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Table 35. Block addresses (continued) Block Protection group 30 Protection group 31 Protection group 32 Protection group 33 Protection group 34 Protection group 35 Protection group 36 Protection group 37 Protection group 38 Protection group 39 Protection group 40 Protection ...
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Table 35. Block addresses (continued) Block Protection group 63 Protection group 64 Protection group 65 Protection group 66 Protection group 67 Protection group 68 Protection group 69 Protection group 70 Protection group 71 Protection group 72 Protection group 73 Protection ...
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Table 35. Block addresses (continued) Block Protection group 96 Protection group 97 Protection group 98 Protection group 99 Protection group 100 Protection group 101 Protection group 102 Protection group 103 Protection group 104 Protection group 105 Protection group 106 Protection ...
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... The common flash interface is a JEDEC approved, standardized data structure that can be read from the flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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Table 38. CFI query system interface information Address Data x16 x8 1Bh 36h 0027h 1Ch 38h 0036h 1Dh 3Ah 00B5h 1Eh 3Ch 00C5h 1Fh 3Eh 0004h 20h 40h 0004h 21h 42h 0009h 22h 44h 0010h 23h 46h 0004h 24h 48h ...
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... Device geometry definition Address Data x16 x8 27h 4Eh 0018h Device size = 2 28h 50h 0002h Flash device interface code description 29h 52h 0000h 2Ah 54h 0006h Maximum number of bytes in multiple-byte program or page= 2 2Bh 56h 0000h Number of Erase block regions. It specifies the number of regions ...
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Table 40. Primary algorithm-specific extended query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h 44h 88h 0033h 45h 8Ah 000Dh 46h 8Ch 0002h 47h 8Eh 0001h 48h 90h 0000h 49h 92h ...
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Table 41. Security code area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX Description 64-bit: unique device number 87/94 ...
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Appendix C Extended memory block The M29W128GH/L has an extra block, the extended memory block, that can be accessed using a dedicated command. This extended memory block is 128 words mode and 256 bytes ...
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C.2 Customer lockable extended memory block A device where the extended memory block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the extended memory block unprotected the customer to program and ...
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Appendix D Flowcharts Figure 30. Write to buffer program flowchart and pseudocode 1. n+1 is the number of addresses to be programmed write to buffer program abort and reset must be issued to return the device in read ...
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Figure 31. Enhanced buffered program flowchart and pseudocode NO NO DQ1 = 1 YES 1. A buffered program abort and reset must be issued to return the device in read mode. 2. When the block address is specified, all the ...
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Revision history Table 43. Document revision history Date Version 24-Nov-2006 0.1 Initial release maximum Chip program time without V RP signal acting as a reset input, unprotection of all the blocks previously protected using a high voltage ...
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Table 43. Document revision history (continued) Date Version Added automotive device grade and automotive qualified information to cover page 6-Oct-2008 6 and order information page. Made the following changes: – New ambient temperature range °C) to ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...