TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet
TXC-06412BROG
Specifications of TXC-06412BROG
Related parts for TXC-06412BROG
TXC-06412BROG Summary of contents
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... Microprocessor Tx/Rx Serial Interface APS Port • 3 Enterprise Drive • Shelton, Connecticut 06484 • Fax: 203-926-9453 • www.transwitch.com ® TXC-06412B DATA SHEET TXC-06412B-MB, Ed. 2 June 2005 DCC Clocks, TERMINAL SIDE Ports Control/Status UTOPIA Level 2 or POS-PHY Level 2 Boundary Scan • USA ...
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... Applications Engineering for current information on this product. U.S. Patents No. 2,695,990; 4,967,405; 5,040,170; 5,142,529; 5,257,261; 5,265,096; 5,331,641; 5,724,362, 2,823,901 U.S. and/or foreign patents issued or pending Copyright 2005 TranSwitch Corporation TranSwitch, TXC, CUBIT, ASPEN Express and PHAST are registered trademarks of TranSwitch Corporation PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - IMPORTANT NOTICE - ...
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... LVPECL I/O Recommendations: ......................................................................................... 58 8.0 Input, Output and Input/Output Parameters ................................................................................ 60 9.0 Timing Characteristics................................................................................................................. 64 10.0 Operation..................................................................................................................................... 91 10.1 Modes.................................................................................................................................. 91 10.1.1 Line Interface Mode .................................................................................................. 91 10.1.2 SDH/SONET Mapping .............................................................................................. 91 10.1.3 System Interface Mode............................................................................................. PHAST-12P Device DATA SHEET TXC-06412B T C ABLE OF ONTENTS PRELIMINARY TXC-06412B-MB, Ed. 2 Page June 2005 ...
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... Transmit DCC Port Interface .................................................................................. 130 11.8.2 Receive DCC Port Interface ................................................................................... 131 11.9 Line Alarm Indication (Ring) Port Interface........................................................................ 132 11.9.1 Internal Line Alarm Indication (Ring) Port Interface................................................ 132 11.9.2 External Line Alarm Indication (Ring) Port Interface............................................... 132 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Per POS-PHY Port Settings............................................................................ 147 Per CLAV Setting............................................................................................ 147 Per POS-PHY Port Status & Alarms ............................................................... 147 Shared Settings for all POS-PHY Ports .......................................................... 148 Per POS-PHY Port Settings............................................................................ 149 Per CLAV Setting............................................................................................ 149 PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... TranSwitch Product, or planning to do so, must register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation issued. They must also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Figure 1. Supported SDH/SONET Mapping .................................................................................................................. 15 2. PHAST-12P TXC-06412B Block Diagram ...................................................................................................... 20 3. PHAST-12P Functional Model ........................................................................................................................ 21 4. PHAST-12P TXC-06412B 376-Lead Plastic Ball Grid Array Package Lead Diagram .................................... TOH Byte Interface ................................................................................................................................... TOH Byte Interface ................................................................................................................................... High Order POH Byte Interface ................................................................................................................ High Order POH Byte Interface................................................................................................................. 67 9. ...
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... POS/ATM Demapper (T_POS_ATM_DEMAPPER) ..................................................................................... 192 49. POS/ATM Demapper Per PHY (T_DMP_DefectsAndCounters) .................................................................. 192 50. POS/ATM Demapper Defects (T_DMP_Defects) ......................................................................................... 193 51. POS/ATM Demapper Performance Counters (T_DMP_PerfCounters) ........................................................ 193 52. POS/ATM Demapper Common Configuration (T_DMP_Common_Config) ................................................. 194 53. POS/ATM Demapper PHY Configuration (T_DMP_Phy_Config) ................................................................. 194 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 L T IST OF ABLES Page ...
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... POH Monitor Common Configuration (T_VCXPM_Common_Config).......................................................... 216 95. POH Monitor Status (T_VCXPM_Common_Status)..................................................................................... 218 96. J1 TTI Stable (T_VCXPM_Report) ............................................................................................................... 218 97. POH Monitor Per Path (T_VCXPM_Status) ................................................................................................. 218 98. POH Monitor Path Status (T_VCXPM_POH_Status) ................................................................................... 219 99. POH Monitor Performance Counters (T_VCXPM_PM) ................................................................................ 219 PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Changed edition number and date. Changed document status from PRODUCT PREVIEW to PRELIMINARY. 3-8 Updated 10 Added 26 Modified Name/Function column for Symbol Reserved. 28 Modified Name/Function column for Symbol LINETXCAP. 28 Modified Name/Function column for table 55 Modified Conditions for Maximum Ratings and Environmental 57 Added last sentence in Requirements. ...
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... Name and Description columns for Offset 0x0000 Bit 2. Table 70, Description column for Offset 0x0000, Bits 12-0 and Table 82, Name and Description columns for Offset 0x0000, Bits 2. PHAST-12P Device DATA SHEET TXC-06412B and APS Interface Monitor. Pulse. streams. Errors. Table 71, PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... POS-PHY Level 2, PMC-971147, issue 5: December 1998 Saturn Compatible Packet over SONET Interface specification for physical layer devices Telcordia GR-253-CORE SONET Common Generic Criteria, Rev 3, September 2000 Telcordia GR-499-CORE Transport Systems Generic Requirements: Common Requirements, Issue 2, December 1998 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 S D TANDARDS OCUMENTATION ® ...
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... STM-4/OC-12 mode: 1+1 or 1:1 APS using two devices connected via the APS port 2. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=3) APS using a single device without APS port 3. STM-1/OC-3 mode: 1+1, 1:1 or 1:n (n<=7) APS using two devices connected via the APS port PHAST-12P Device DATA SHEET TXC-06412B O VERVIEW PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... The application software calls the driver functions to configure, control and manage the PHAST-12P device. The device driver insulates the application from the internal details of the device register usage and provides a higher level of abstraction. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... AU-4 AUG-1 STS-3c STS-3c SPE x3 VC-3 AU-3 STS-1 STS-1 SPE PHAST-12P Device DATA SHEET TXC-06412B 1.0 F EATURES X=2 STS-6c Payload X=3 STS-9c Payload C-4-4c C-4-Xc X=4 STS-12c STS-3c-Xc Payload Payload C-4 STS-3c Payload C-3 STS-1 Payload PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... B2 BIP-24/96 insertion and monitoring • Degraded signal and excessive bit error detection • Block and bit error performance monitoring counters • D4-D12 DCC can be accessible via the DCC port • Insertion and monitoring of remote information (RDI, REI) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Features - - ...
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... Each individual output channel can be forced to source an AIS or unequipped mainte- nance signal 1.8 ATM CELL HANDLING • Egress: ATM cell demapping from SDH/SONET streams • Cell delineation including header error detection and correction • HEC checking Features - PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
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... Maximum clock speed 50 MHz • Cell level handshaking for up to twelve high order path cell streams • Single-PHY or multi-PHY mode • Status indication modes PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Features - - ...
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... Interrupt mask bits for controlling generation of hardware interrupt requests 1.13 TESTING • Line loopbacks • High order path loopbacks via the cross-connect • Boundary scan 1.14 DEVICE DRIVER • Device configuration • Fault monitoring • Performance monitoring Features - PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
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... PRBS Generator TOH Port POH Ring Port Generator Pointer Generator ATM/PPP Ingress UTOPIA POS-PHY UTOPIA/POS-PHY Level 2 Figure 2. PHAST-12P TXC-06412B Block Diagram PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Block Diagram - - 2.0 B APS Port @ 622.08 Mbit/s Clock Clock/Data Synthesis Recovery TOH Port APS Port ...
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... Note: Additional information regarding Functional Diagram of the PHAST-12P can be found in ITU-T G.783 Standards Documentation. Figure 3. PHAST-12P Functional Model Functional Model - 3.0 F UNCTIONAL APS_TT APS/MSnP_A MSnP_TT Sn_TTm MSn/Sn_A Sn_C Sn_TT POS-PHY UTOPIA PHAST-12P Device DATA SHEET TXC-06412B M ODEL Sn_TTm PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... The PHAST-12P performs high order pointer processing on the H1/H2 bytes from the receive APS port. The high order path containers are retimed to the local system clock. High order POH monitoring is performed on all received high order path containers for SNC/P and UPSR applications. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Block Diagram Description - - 4 ...
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... For Test purposes, a PRBS pattern can be generated and inserted on a particular path by the PHAST-12P. PRBS can be analyzed for bit errors on the receive side Block Diagram Description - PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Digital +1.8 V Supply +/-5% VDD18, 24 places Digital I/O +3.3 V Supply +/-5% VDD33, 24 places VSS Figure 4. PHAST-12P TXC-06412B 376-Lead Plastic Ball Grid Array Package Lead Diagram PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Diagram - - 5 Note: This is the bottom view. The leads are solder balls. See Figure 51 for package information ...
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... Digital Core 1.8V & Digital I/O 3.3V returns P Rx PLL / Clock Recovery & Rx LVPECL analog 1.8V return P Tx PLL / Clock Synthesis & Tx LVPECL analog 1.8V return P LVPECL driver & pre-drive analog 3.3V returns PHAST-12P Device DATA SHEET TXC-06412B D ESCRIPTIONS PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... LINERXDATA3P W15 LINERXDATA3N Y16 LINERXDATA4P AB18 LINERXDATA4N AB19 LINERXSIGDET1 AA18 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P No Connect: These leads are not to be con- nected, and must be left floating. Connection lead may impair performance or cause Y20 damage to the device. NC leads that are currently ...
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... LVPECL Serial SDH/SONET Transmit Data #4: 155.52 Mbit/s bit- serial data to electro/optical transceivers. Not valid in STM-4/OC-12 mode. PHAST-12P Device DATA SHEET TXC-06412B Name/Function from the serial data stream from the serial data stream from the serial data stream from the serial data stream Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... The clock rate is programmable to be either 19.44 or 77.76 MHz. The frequency tolerance for this clock is ± 20 ppm. The maximum allowed jitter on this clock should be confined to the same limits as indicated below for the REFTXCLK2P/ REFTXCLK2N leads. Name/Function STM-1/OC-3 STM-4/OC-12 ...
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... LVTTL Transmit Reference Frame Sync: Optional 8 kHz reference frame sync pulse. If present, this input must be synchronous to LINETXCLK and shall be at least 1 77.76 MHz clock cycle wide = 12.86 ns LVCMOS System Reference Frame Sync: 8 kHz reference frame 8mA sync pulse ...
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... DCCRXDATA4 V3 O DCCRXCLK1 V1 O DCCRXCLK2 W1 O DCCRXCLK3 T4 O PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - Type Name/Function LVCMOS Receive DCC Data #1: Bit-serial data from the TOH moni- 4mA tor of receive line interface # external LAPD inter- face controller or similar device. This data can be optionally selected to provide D1-D3 (RS/ Section DCC) or D4-D12 (MS/Line DCC) ...
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... Transmit DCC Clock #2: The DCCTXDATA2 signal is 8mA clocked into the PHAST-12P on negative transitions of this clock. If MS/Line DCC is selected for DCCTXDATA2, the fre- quency is 576 kHz, if RS/Section DCC is selected for DCCTXDATA2, the frequency is 192 kHz. PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... PHAST-12P Device DATA SHEET TXC-06412B Symbol Lead No. I/O/P DCCTXCLK3 R3 O DCCTXCLK4 T2 O PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - Type Name/Function LVCMOS Transmit DCC Clock #3: The DCCTXDATA3 signal is 8mA clocked into the PHAST-12P on negative transitions of this clock. If MS/Line DCC is selected for DCCTXDATA3, the fre- quency is 576 kHz, if RS/Section DCC is selected for DCCTXDATA3, the frequency is 192 kHz ...
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... PPUTTXADDR to initiate writes to the Tx FIFOs. Selec- tion phase when PPUTTXENB is asserted high and transfer phase when PPUTTXENB is asserted low. Dur- ing transfer phase PPUTTXADDR is used for polling. UTOPIA Standard notation: TxEnb* PHAST-12P Device DATA SHEET TXC-06412B Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... It is driven when a matching PHY address is presented on PPUTTXADDR. Tristated when either the null-PHY address or a not matching PHY address is presented on PPUTTXADDR. UTOPIA Standard notation: TxClav[3:0] I LVTTL Not Applicable Inputs: These leads must be tied to VSS. O(T) ...
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... Both direct status and multiplexed status are supported driven when a matching PHY address is presented on PPUTRXADDR. Tristated when either the null-PHY address or a not matching PHY address is presented on PPUTRXADDR. UTOPIA Standard notation: RxClav[3:0] PHAST-12P Device DATA SHEET TXC-06412B Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... PPUTTXDATA06 D18 PPUTTXDATA05 A21 PPUTTXDATA04 B19 PPUTTXDATA03 C18 PPUTTXDATA02 D17 PPUTTXDATA01 A20 PPUTTXDATA00 B18 PPUTTXPRTY D22 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type O(T) LVCMOS Not Applicable Outputs: These leads must be left 16mA unconnected. I/O/P Type I LVTTL Transmit POS-PHY Clock: This clock is used for the Transmit POS-PHY interface ...
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... Tristated when PPUTTXENB is asserted high in the pre- vious cycle, or when either the null-PHY address or a not matching PHY address has been selected. POS-PHY Standard notation: STPA PHAST-12P Device DATA SHEET TXC-06412B Name/Function minimum number of free words PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... PPUTRXCLK C11 PPUTRXADDR4 C12 PPUTRXADDR3 B12 PPUTRXADDR2 A12 PPUTRXADDR1 A11 PPUTRXADDR0 B11 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type O(T) LVCMOS Polled-PHY Transmit Packet Available: Transitions 24mA high when a predefined (user programmable) number of free words is available in the polled Tx FIFO. Once high, ...
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... Receive Start of Packet: Indicates the first word of a 16mA packet. Tristated when PPUTRXENB is asserted high in the previous cycle, or when either the null-PHY address or a not matching PHY address has been selected. POS-PHY Standard notation: RSOP PHAST-12P Device DATA SHEET TXC-06412B Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... DATA SHEET TXC-06412B Symbol Lead No. PPRXEOP C14 PPRXERR D13 A14 PPUTRXENB PPRXVAL B14 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type O(T) LVCMOS Receive End of Packet: Indicates the last word of a 16mA packet. Note: Can be asserted high together with PPUTRX- SOPC, in case byte packet ...
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... PHAST-12P device, it must be tied to VSS. I LVTTL Transmit Line Ring Port Frame Sync: An active high, one LRPTXCLK clock-cycle wide frame sync pulse that identifies the first bit in the data stream present on LRPTXDATA. When this lead is not connected to LRPRXFS of a mate PHAST-12P device, it must be tied to VSS. ...
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... PHAST-12P device, it must be tied to VSS. I LVTTL Transmit HO Ring Port Frame Sync: An active high, one PRPTXCLK clock-cycle wide frame sync pulse that identifies the first bit in the data stream present on PRPTXDATA. When this lead is not connected to LRPRXFS of a mate PHAST-12P device, it must be tied to VSS. ...
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... TOHTXDATA is clocked in on the rising edge of this clock. Its frequency is 77.76 MHz. LVCMOS Transmit TOH Port Address Latch Enable: An active 8mA high, 10 TOHTXCLK clock-cycle wide pulse indicating that a valid address is present on TOHTXADDR. LVCMOS Transmit TOH Port Address: The 10 consecutive states 8mA ...
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... POHTXDATA is clocked in on the rising edge of this clock. Its frequency is 77.76 MHz. O LVCMOS Transmit HO POH Port Address Latch Enable: An 8mA active high, 8 POHTXCLK clock-cycle wide pulse indicat- ing that a valid address is present on POHTXADDR. O LVCMOS Transmit HO POH Port Address: The 8 consecutive 8mA ...
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... Lead Descriptions - Type LVCMOS Transmit HO POH Port Data Latch Enable: An active 8mA high, 8 POHTXCLK clock-cycle wide pulse indicating that valid data is present on POHTXDATA. I LVTTL Transmit HO POH Port Data: The value of the High Order POH byte requested by POHTXADDR is clocked in as the 8 consecutive states while POHTXDLE is high. ...
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... MPINTLEVEL A2 I MPACKLEVEL D5 I Note: The Generic Intel, Generic Motorola, Motorola MPC860 and Motorola MPC8260 Local Bus - Host Processor interfaces are shared on the same leads. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - Type Name/Function LVTTL Microprocessor Interface Select: These leads select the Host ...
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... PHAST-12P through a read or write cycle. Intel notation LVTTL Read Strobe (Active low): This active low lead initiates a read transfer between the host processor and the PHAST-12P. Intel notation: RD PHAST-12P Device DATA SHEET TXC-06412B Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... B2 MPA05 E2 MPA04 F3 MPA03 G4 MPA02 D1 MPA01 E1 MPA00 F2 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type I LVTTL Write Strobe (Active Low): This active low lead initiates a write transfer between the host processor and the PHAST-12P. Intel notation: WR O(T) LVCMOS Ready: For a write access, an active edge on this lead indi- ...
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... Active level depends on MPACKLEVEL. Motorola notation: DSACK O LVCMOS Interrupt Request: This lead signals an interrupt request 8mA to the host processor. Active level depends on MPINTLEVEL. PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... J2 MPD03 K3 MPD02 J1 MPD01 K2 MPD00 L4 K1 MPSEL L3 MPTS PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type I LVTTL Microprocessor Clock: This lead is the clock sourced by the microprocessor being interfaced to this device. Its max. frequency is 50 MHz. Motorola MPC860 notation: CLK I LVTTL Address Bus: These leads are the address bus used by the host processor for accessing the PHAST-12P for a read or write cycle ...
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... LVTTL Local Address Bus: These leads are the address bus used by the host processor for accessing the PHAST-12P for a read or write cycle. MPA13 is the most significant bit in the location’s address. Motorola MPC8260 Notation: L_A[ ] PHAST-12P Device DATA SHEET TXC-06412B Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... I MPTS L2 I MPWR L1 O(T) LVCMOS MPACK B3 O MPINTR PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - LVTTL/ Local Data Bus: These leads are the bidirectional data bus LVCMOS used for transferring data between the PHAST-12P and the 8mA host processor. MPD15 is the most significant bit. ...
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... This lead must be tied to VSS. I LVTTL Receive Line Bypass Sequence: For TranSwitch testing purposes. This lead must be tied to VSS. I LVTTL Receive Line Bypass Data: For TranSwitch testing purposes. These leads must be tied to VSS. PHAST-12P Device DATA SHEET TXC-06412B Name/Function Name/Function PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... AA4 BYPTXDATA0 AB2 TEST Symbol Lead No. DEVHIGHZ C4 TEST1 C3 PLLBYPASS A5 SCANEN D7 SCANMODE C6 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type I LVTTL Transmit Line Bypass Clock: For TranSwitch testing purposes. This lead must be tied to VSS. O LVCMOS Transmit Line Bypass C1 Indication: 8mA For TranSwitch testing purposes. ...
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... Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the “CAUTION” label on the drypack bag in which devices are supplied. 3. Test method for ESD per JEDEC JESD22-A114C.01. 4. Device core is 1.8V only. 5. All LVDS and LVPECL inputs, LINERXCAP and LINETXCAP are excluded. 7.2 THERMAL CHARACTERISTICS Parameter Thermal resistance - junction to ambient 7 ...
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... Typical values are based on measurements made with nominal voltages Maximum values are based on measurements made at maximum voltages All four line interfaces are operational in STM-1/OC-3 mode, and the APS port is operational. 3. All measurements for the Parameter P PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Selected Parameter Values - ...
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... Line side. The recommendation is to have separate 1.8V supplies for VDDA18TPA and VDDA18RPA, each one carefully filtered.The power supply noise requirement for both VDDA18TPA and VDDA18RPA is 20 mVpp max Selected Parameter Values - PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Provide enough resistors in the schematic. Some of them may not be required, and can be treated as ‘do not install’. To achieve optimal jitter performance recommended to connect a differential oscillator to REFTXCLK2P/N (LVPECL), instead of a single-ended to REFTXCLK1 (LVTTL). PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Selected Parameter Values ...
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... Unused LVDS inputs can be left floating (no resistors required). Unused LVDS outputs can be left floating (no resistors required Selected Parameter Values - cable careful implementation, cable length can PHAST-12P Device DATA SHEET TXC-06412B termination resistor between resistor on the board, between PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Rx input differential voltage input offset voltage iS Input/Output Parameters for LVDS Parameter Min 0.925 1.125 0 -0 RiN PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 , O NPUT UTPUT AND Typ Max Unit 1.114 V 1.769 V 0.657 V 1.44 V TBD V 2.4 V Typ Max Unit 1.475 V V 0.4 V 1.275 V 140 Ohm 1 ...
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... DD33 DD33 SS Test Conditions 3.14 < V < 3.46 DD33 3.14 < V < 3.46 DD33 DD33 Test Conditions 3.14 < V < 3.46 DD33 3.14 < V < 3.46 DD33 DD33 Test Conditions V = 3.15 -24 DD33 3.15 DD33 LOAD LOAD input . DD33 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... Output capacitance Output Parameters for LVCMOS 16mA Parameter Min Output capacitance V 2 -16 OH 1.28 tRISE 1.04 tFALL Leakage tristate Note: Open Drain requires use of a 4.7 k PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - Typ Max Unit TBD 3.38 ns 3.22 ns ±15 A Typ Max Unit V 0 ...
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... V < 3.45 DD33 3.15 < V < 3.45 DD33 0 to 3.3 V input V = 3.15 -16 DD33 3.15 DD33 LOAD LOAD Test Conditions 3.15 < V < 3.45 DD33 3.15 < V < 3.45 DD33 0 to 3.3 V input V = 3.15 DD33 3.15 DD33 LOAD LOAD PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
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... TOHRXDLE (Output) TOHRXDATA (Output Load Parameter TOHRXCLK clock period TOHRXCLK clock pulse width TOHRXALE/TOHRXADDR out valid delay from TOHRXCLK TOHRXDLE/TOHRXDATA out valid delay from TOHRXCLK PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - 9.0 T IMING Figure 5. RX TOH Byte Interface t PWH ADDRESS ...
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... TOHTXDATA (Input Load Parameter TOHTXCLK clock period TOHTXCLK clock pulse width TOHTXALE/TOHTXADDR out valid delay from TOHTXCLK TOHTXDLE out valid delay from TOHTXCLK TOHTXDATA setup time before TOHTXCLK TOHTXDATA hold time after TOHTXCLK Timing Characteristics - Figure 6. TX TOH Byte Interface ...
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... POHRXADDR A7 (Output) t D(1) POHRXDLE (Output) POHRXDATA (Output Load Parameter POHRXCLK clock period POHRXCLK clock pulse width POHRXALE/POHRXADDR out valid delay from POHRXCLK POHRXDLE/POHRXDATA out valid delay from POHRXCLK PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - t PWH A6 A0 Symbol t CYC t PWH t D(1) ...
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... D(1) POHTXDLE (Output) POHTXDATA (Input Load Parameter POHTXCLK clock period POHTXCLK clock pulse width POHTXALE/POHTXADDR out valid delay from POHTXCLK POHTXDLE out valid delay from POHTXCLK POHTXDATA setup time before POHTXCLK POHTXDATA hold time after POHTXCLK Timing Characteristics - t PWH D(2) ...
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... DATA SHEET TXC-06412B LRPRXCLK (Output) LRPRXFS (Output) .... LRPRXDATA (Output Load Parameter LRPRXCLK clock period LRPRXCLK clock pulse width LRPRXFS/LRPRXDATA out valid delay from LRPRXCLK PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - Figure 9. RX Line Ring Port Interface t CYC last bit bit # Symbol t ...
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... Figure 10. TX Line Ring Port Interface LRPTXCLK (Input) LRPTXFS (Input) .... LRPTXDATA (Input Load Parameter LRPTXCLK clock period LRPTXCLK clock pulse width LRPTXFS/LRPTXDATA setup time before LRPTXCLK LRPTXFS/LRPTXDATA hold time after LRPTXCLK Timing Characteristics - last bit bit #1 bit # Symbol Min t CYC t 40 ...
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... Figure 11. RX Path Alarm Indication Port Interface PRPRXCLK (Output) PRPRXFS (Output) .... PRPRXDATA (Output Load Parameter PRPRXCLK clock period PRPRXCLK clock pulse width PRPRXFS/PRPRXDATA out valid delay from PRPRXCLK PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - t CYC t PWH last bit bit #1 bit #2 t ...
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... Figure 12. TX Path Alarm Indication Port Interface PRPTXCLK (Input) PRPTXFS (Input) .... PRPTXDATA (Input Load Parameter PRPTXCLK clock period PRPTXCLK clock pulse width PRPTXFS/PRPTXDATA setup time before PRPTXCLK PRPTXFS/PRPTXDATA hold time after PRPTXCLK Timing Characteristics - last bit bit #1 bit # Symbol Min t CYC ...
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... PHAST-12P Device DATA SHEET TXC-06412B Figure 13. Relationship between the External Frame Reference Pulse (REFTXFS) and the generated Internal Frame Reference Pulse (REFSYSFS) a. REFTXFS synchronous to rising edge of LINETXCLK (at 77.76 MHz) t (Output) CYC LINETXCLK (Output) REFTXFS (Input) REFSYSFS (Output) b. REFTXFS synchronous to falling edge of LINETXCLK (at 77.76 MHz) ...
Page 73
... Notes: 1. The relationship between the External Frame Reference pulse input (REFTXFS lead) and System Frame Reference Pulse is only useful when LINETXCLK is configured to 77.76 MHz. Because of this the period of LINETXCLK used in the timing diagrams above is 12.86 ns additional offset 9719 clock cycles (77.76 MHz clock) can be inserted between REFTXFS and REFSYSFS by ...
Page 74
... Figure 14. Microprocessor Interface: Generic Intel Mode Write Cycle t SU1 A t SU2 RD t SU3 CS t SU4 RDY CLK Note: MPACK (RDY) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - Generic Intel - Host Processor Interface ...
Page 75
... Delay from rising edge WR to inactive edge RDY Delay from RDY going inactive to RDY going in tristate Delay from rising edge WR to RDY going in tristate WR inactive pulse width Response latency CS inactive pulse width PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 76
... Figure 15. Microprocessor Interface: Generic Intel Mode Read Cycle t SU1 A t SU2 WR t SU3 RDY CLK Note: MPACK (RDY) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - SU4 Generic Intel - Host Processor Interface ...
Page 77
... Delay from RDY going inactive to RDY going in tristate Delay from rising edge RD to RDY going in tristate RD inactive pulse width Response latency Delay from falling edge driving Delay from rising edge going in tristate CS inactive pulse width PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 78
... Figure 16. Microprocessor Interface: Generic Motorola Mode Write Cycle t SU1 A t SU2 R/W t SU3 CS t SU4 DSACK CLK Note: MPACK (DSACK) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - Generic Motorola - Host Processor Interface ...
Page 79
... Delay from rising edge DS to inactive edge DSACK Delay from DSACK going inactive to DSACK going in tristate Delay from rising edge DS to DSACK going in tristate DS inactive pulse width Response latency CS inactive pulse width PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 80
... Figure 17. Microprocessor Interface: Generic Motorola Mode Read Cycle t SU1 A t SU2 R/W t SU3 DSACK CLK Note: MPACK (DSACK) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - SU4 Generic Motorola - Host Processor Interface ...
Page 81
... Delay from DSACK going inactive to DSACK going in tristate Delay from rising edge DS to DSACK going in tristate DS inactive pulse width Response latency Delay from falling edge driving Delay from rising edge going in tristate CS inactive pulse width PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 82
... PHAST-12P Device DATA SHEET TXC-06412B Figure 18. Microprocessor Interface: Motorola MPC860 Mode Write Cycle CLK t SU1 A t SU2 RD/WR t SU3 SU4 See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - t SU5 Motorola MPC860 - Host Processor Interface for the mapping to I/O leads. ...
Page 83
... Delay from rising edge CLK to active edge TA Delay from rising edge CLK to inactive edge TA Delay from TA going inactive to TA going in tristate Delay from rising edge CLK to TA going in tristate Maximum response latency PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 84
... PHAST-12P Device DATA SHEET TXC-06412B Figure 19. Microprocessor Interface: Motorola MPC860 Mode Read Cycle CLK t SU1 A t SU2 RD/WR t SU3 SU4 See the Lead Description table on PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - t SU6 Motorola MPC860 - Host Processor Interface for the mapping to I/O leads. ...
Page 85
... Delay from TA going inactive to TA going in tristate Delay from rising edge CLK to TA going in tristate Maximum response latency Setup time rising edge CLK Hold time of D going in tristate to rising edge CLK PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 86
... Figure 20. Microprocessor Interface: Motorola MPC8260 Local Bus Mode Write Cycle CLK t SU1 L_A t SU2 LWR t SU3 CS t SU5 LCL_D t D1 LGTA 1. See the Lead Description table on I/O leads. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - Motorola MPC8260 Local Bus - Host Processor Interface ...
Page 87
... Delay from rising edge CLK to active edge LGTA Delay from rising edge CLK to inactive edge LGTA Delay from LGTA going inactive to LGTA going in tristate Delay from rising edge CLK to LGTA going in tristate Maximum response latency PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 88
... PHAST-12P Device DATA SHEET TXC-06412B Figure 21. Microprocessor Interface: Motorola MPC8260 Local Bus Mode Read Cycle CLK t SU1 L_A t SU2 LWR t SU3 CS LCL_D LGTA 1. See the Lead Description table on I/O leads. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - SU6 Motorola MPC8260 Local Bus - Host Processor Interface ...
Page 89
... Delay from LGTA going inactive to LGTA going in tristate Delay from rising edge CLK to LGTA going in tristate Maximum response latency Setup time D to rising edge CLK Hold time of D going in tristate to rising edge CLK PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 90
... TCK clock duty cycle t PWH/tCYC TMS setup time to TCK TMS hold time after TCK TDI setup time to TCK TDI hold time after TCK TDO delay from TCK TRS pulse width PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Timing Characteristics - - Figure 22. Boundary Scan Timing t H(1) ...
Page 91
... POH column VC-4-Xc resp. STS-Nc contiguous concatenated container. The AUG-1 time slot is a slave (i.e., it does not carry the POH column VC-4-Xc resp. STS-Nc contiguous concatenated container. PHAST-12P Device DATA SHEET TXC-06412B PERATION Figure 1. The mapping of PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 92
... System side interface operates in UTOPIA Level 2 mode. 10.2 CLOCK ARCHITECTURE The PHAST-12P’s internal Transmit Clock synthesizer generates, using a selectable Tx timebase, a high-speed Transmit Clock, running at 622.08 MHz. The System Clock, running at 77.76 MHz divided-down version of this high-speed Transmit Clock. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - AUG-1 ...
Page 93
... PHY clocks as inputs. These clocks are generated by the ATM/Link layer device. Clock boundary crossings from/to the System Clock are done in Rx and Tx Cell/Packet FIFOs. The System Clock is available on an output lead: LINETXCLK, optionally divided down to 19.44 MHz. The PHAST-12P’s internal Clock Recovery units, operating on the four SDH/SONET Receive Line interfaces and the Receive APS Port generate five recovered clocks: one for each channel ...
Page 94
... PHAST-12P Device DATA SHEET TXC-06412B • Either one of the two external Tx clock sources: REFTXCLK1 or REFTXCLK2P/N (Exter- nal Timing) (control field TxRefSelect, see tions) • The external Rx clock source: REFRXCLOCK (Line/Loop - Timing) (control field RxRef- Select, see Table 69 In case REFTXCLOCK2P/N is used as Rx timebase, the 622.08 MHz frequency (bypass mode) is not supported ...
Page 95
... POS-PHY POS-PHY PPUTTXCLK PPUTRXCLK UTOPIA/POS-PHY Level Operation - APS Port @ 622.08 Mbit/s APS Port Transmit K1/K2 APS LINERXCLK1..4 High Order Path Cross Connect PHAST-12P Device DATA SHEET TXC-06412B APS Port Receive K1/K2 APS Pointer Tracking APSRXCLK Retimer PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 96
... MPCLK System Clock (=LINETXCLK) MPCLK System Clock (= LINETXCLK) LINERXCLK1 MPCLK System Clock (= LINETXCLK) LINERXCLK2 MPCLK System Clock (= LINETXCLK) LINERXCLK3 MPCLK System Clock (= LINETXCLK) LINERXCLK4 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - Memory Maps and Bit Descriptions). Blocks Global Control Reset Generator Interrupt ...
Page 97
... System Clock (= LINETXCLK) APSRXCLK MPCLK System Clock (= LINETXCLK) PPUTTXCLK MPCLK System Clock (= LINETXCLK) PPUTRXCLK 10.2.2 Loss of Clock Detection All clocks, except the microprocessor clock, are monitored for Loss of Clock. The clock to be monitored is divided by LocDivider + 1. Loss of Clock is detected as follows: • Entry: when LOC_EntryThreshold microprocessor clock cycles have passed without transitions on the divided clock to be monitored • ...
Page 98
... Operation is halted so the device can be configured in a clean way. Once the configuration is done, DeviceInitialized field in Global Control can be set to 1 and the device will start its normal operation. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation ...
Page 99
... PLL Select Rx PLL Reference Clock Fre- quency 0x0 0x0 N/A Select Line Rate of Reference Channel STM-4/OC-12 Mode STM-1/OC-3 Mode 0x0E PHAST-12P Device DATA SHEET TXC-06412B Line Timing 0x1 N/A N/A 0x0 0x0 STM-4/OC-12 Mode 0x0F 0x0E PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 100
... PHAST-12P Device DATA SHEET TXC-06412B • Write 0x00 to TxRefClock2 PadPowerDown register (Address 0x3A34) if REFTXCLK2 is used as reference clock • Power up the Rx pads: RxPadPowerDown register (Address 0x3A30) • Write 0x00 to RxPowerDown1 register (Address 0x3A54) • Write 0x00 to RxPowerDown2 register (Address 0x3A56) • Write 0x00 to TxPowerDown register (Address 0x3A50) • ...
Page 101
... PRBS generator and analyzer before (re-)configuring them. Important Notes: 1. Although the PRBS bit error counter is mapped in the memory map of the CDR/CS block, the System clock (LINETXCLK) must be available when reading this counter may contain errors not recalculated on the PRBS data ...
Page 102
... Clock recovery and synthesis are integrated. The device’s system clock is the time base for the transmit APS interface output. The APS port interface can be powered down via a memory mapped register. The APS Interface characteristic information consists of: PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - ...
Page 103
... Rx K1, Tx K1, Rx K2, Tx K2, Status and Request are inserted according to the APS pro- tocol • AU Pointer bytes are passed • Unused bytes are set to 0x00 Operation - Status Req PHAST-12P Device DATA SHEET TXC-06412B 270 Payload PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 104
... A single or 16 byte Trail Trace Identifier will be inserted in the J0 byte • The interleave depth coordinate can be inserted in the Z0 bytes for backwards compati- bility. Note the Z0 bytes need to be carefully chosen in order to guarantee enough transi- tions on the first TOH row. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - ...
Page 105
... The PHAST-12P RSOH Monitor will insert AIS per line interface towards the MSOH Monitor according to the following expression: aAIS [line Operation - = dTIM * not TIM_AIS_Insert_Disable [line] + RSOH_AIS_Force [line] PHAST-12P Device DATA SHEET TXC-06412B [line] PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 106
... The software readable B2 bytes have a special behavior, in that the transmitted bytes represent the error mask (difference between calculated and received bytes). • The error count per frame will be forwarded to the internal and external line ring ports as REI indication for the mate TOH generator PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - ...
Page 107
... EXC_AIS_Insert_Disable [line] + dSSF * not SSF_AIS_Insert_Disable [line] + MSOH_AIS_Force [line] = dAIS * not AIS_RDI_Insert_Disable [line] [line] + dEXC * not EXC_RDI_Insert_Disable [line] + dSSF * not SSF_RDI_Insert_Disable [line] + MSOH_AIS_Force [line] PHAST-12P Device DATA SHEET TXC-06412B [line] [line] [line] [line] [line] [line] PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 108
... APS Port • POH Termination Each bus will transport synchronous payload containers equivalent to a STM-4/OC-12 rate, i.e AU-3/VC-3/STS-1’ four VC-4/STS-3c’s SPE two STS-6c’s, one STS-9c, one VC-4-4c/STS-12c SPE, or combinations thereof. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - Description ...
Page 109
... FSM indications from the protection line to the worker lines. The FSM indications include Operation - Extra Traffic To/From POH Monitor/Generator PHAST-12P Device DATA SHEET TXC-06412B Cross Connect Switch y Bridge Squelch Extra Protected Traffic Traffic PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 110
... SF RxAPS Read Only Read/Write The Tx APS Port interface sends the synchronous payload data from this PHAST-12P to its mate PHAST-12P. It also allows the in-band forwarding of RxAPS, TxAPS, Status and Request: PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - Tx APS Port Rx APS Port Tx APS Port ...
Page 111
... STM-4 SONET Lite Port. Important limitation to know about this: the incoming B2 bytes are NOT processed by the APS Monitor. Remark also the APS port has LVDS I/Os while the Line Ports has LVPECL I/ Operation - “APS Interface” on page PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B 102, the June 2005 ...
Page 112
... When the APS FSM detects a failure of the Worker line the cross connect of the Worker PHAST-12P performs the protection switch. It connects the receive protected traffic to the Receive APS Port interface which transports the payload of the received Protection line. W TxApsPort y RxApsPort W Protected Traffic PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - P W TxApsPort y ...
Page 113
... Protection line. The unprotected extra traffic is no longer available and will be squelched. W TxApsPort y RxApsPort W Protected Traffic Operation - TxApsPort y TxApsPort Switch RxApsPort RxApsPort W E Protected Traffic Figure 27. STM-4/OC-12, 1:1 APS PHAST-12P Device DATA SHEET TXC-06412B P TxApsPort RxApsPort Bridge Squelch E PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 114
... Worker Transmit lines to their Protection Transmit lines over one of the APS Port interfaces. The received protection payload of the four lines is available on the other APS Port interface Cross Connect device # Protected Traffic To/From POH Monitor/Generator Figure 28. STM-1/OC-3, 1+1 APS Idle State PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - W4 PHAST-12P #1 PHAST-12P #2 RxApsPort TxApsPort y RxApsPort TxApsPort ...
Page 115
... Receive APS Port interface Cross Connect Switch device # Protected Traffic To/From POH Monitor/Generator Figure 29. STM-1/OC-3, 1+1 APS Switch State Operation - W4 PHAST-12P #1 PHAST-12P #2 RxApsPort TxApsPort y TxApsPort RxApsPort W4 PHAST-12P Device DATA SHEET TXC-06412B Figure 29, the Cross Connect device #2 PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 116
... This allows unprotected extra traffic to be transported over a Protection line while there is no protection request active at that line Cross Connect device # Protected Traffic To/From POH Monitor/Generator Figure 30. STM-1/OC-3, 1:1 APS Idle State PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - W4 PHAST-12P #1 PHAST-12P #2 TxApsPort RxApsPort y TxApsPort RxApsPort ...
Page 117
... W2 W3 Protected Traffic To/From POH Monitor/Generator Figure 31. STM-1/OC-3, 1:1 APS Switch State Operation - W4 PHAST-12P #1 PHAST-12P #2 RxApsPort TxApsPort y RxApsPort TxApsPort W4 PHAST-12P Device DATA SHEET TXC-06412B Figure 31, the Bridge Cross Connect y device # Squelch Extra Traffic To/From POH Monitor/Generator PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 118
... Figure 32 shows an example of a 1:n (n=7) APS protection architecture in STM-1/OC-3 mode using two PHAST-12P devices Cross Connect device # Protected Traffic To/From POH Monitor/Generator Figure 32. STM-1/OC-3, 1:7 APS Idle State PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - W4 PHAST-12P #1 PHAST-12P #2 TxApsPort RxApsPort y TxApsPort RxApsPort ...
Page 119
... Protected Traffic To/From POH Monitor/Generator Figure 33. STM-1/OC-3, 1:7 APS Switch State Operation - W4 PHAST-12P #1 PHAST-12P #2 RxApsPort TxApsPort y TxApsPort RxApsPort W4 PHAST-12P Device DATA SHEET TXC-06412B Figure 33, the Bridge Cross Connect device #2 Squelch Extra Traffic Protected Traffic To/From POH Monitor/Generator PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 120
... In case the failed line is terminated in PHAST-12P #2 itself, the cross-connect of that PHAST- 12P #2 will perform the protection switch without use of the APS port Cross Connect device # Protected Traffic To/From POH Monitor/Generator Figure 34. STM-1/OC-3, 1:7 APS Switch State PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Operation - - W4 PHAST-12P #1 PHAST-12P #2 TxApsPort RxApsPort y RxApsPort TxApsPort ...
Page 121
... P T OINTER RACKING P AND OINTER = dAIS * not AU_AIS_AIS_Insert_Disable [path] + dLOP * not LOP_AIS_Insert_Disable [path] + dTSF * not TSF_AIS_Insert_Disable [path] + FifoError * not [path] FifoError_AIS_Insert_Disable + AIS_Force [path] PHAST-12P Device DATA SHEET TXC-06412B , R ETIMING G ENERATION PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 122
... Frame Reference Pulse internally. The (generated) System Frame Reference Pulse is available via the REFSYSFS lead. Generator REFTXFS Generator REFSYSFS ATM/PPP Figure 35. Frame Reference Pulse Generation PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Pointer Tracking Retimer High Order Path Cross Connect POH Pointer Ingress ...
Page 123
... The center zone is called Dead Zone and is 5 words wide. In this zone, the FIFO is at half filling and no pointer adjustments will be made Figure 36. FIFO center Zone 2 Zone 1 Zone 2 Leak Slow Dead Zone Leak Slow PHAST-12P Device DATA SHEET TXC-06412B Figure 13 Zone 3 Zone 4 Leak Fast Leak Immediate PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 124
... The internal or external ring port • The REI will be inserted into the G1 byte • Per high order path the RDI can be sourced from • The transmit POH RAM • The transmit POH byte interface • The internal or external ring port PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - ...
Page 125
... Optionally insertion of VC-AIS, resulting in the insertion of all 1’s in the entire VC • Optionally insertion of Unequipped, resulting in the insertion of all 0’s in the entire E-RDI indication b5 Server 1 Connectivity 1 Payload 0 None 0 E-RDI indication b5 Server 1 Connectivity 1 Payload 0 None 0 PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 126
... Optionally bit errors will be counted • During incoming SSF, the counter is not updated • Received RDI (3 bit) is debounced on a configurable number of frames basis (ETSI Telcordia: 10) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 “Trail Trace Identifier Process” on page 151. “BER Supervision for B2/B3” on page “ ...
Page 127
... TIM_AIS_Insert_Disable [path] = AI_TSF [path] + dPLM * not PLM_AIS_Insert_Disable [path] + AIS_Force [path] = dSSF * not SSF_RDI_Insert_Disable [path] = dUNEQ * not UNEQ_RDI_Insert_Disable [path] + dTIM * not TIM_RDI_Insert_Disable [path] = dPLM * not PLM_RDI_Insert_Disable [path] + dLCD * not LCD_RDI_Insert_Disable [path] PHAST-12P Device DATA SHEET TXC-06412B [path] PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 128
... PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 = aE-RDI-S [path] + aE-RDI-C [path] dSSF [path] dAIS * not AIS_SSF_Contribution_Disable [path] dAIS [path] dUNEQ [path] (not dSSF + SSF_UNEQ_Inhibit_Disable) [path] (dTTIZERO + TTIZERO_UNEQ_Contribution_Disable) [path] (dTIM + TIM_UNEQ_Contribution_Disable) [path] dTIM ...
Page 129
... Note the BIP bytes (B1, B2) have a special meaning, these can be used as an error mask on the calculated BIP. The Transmit TOH Port consists of following leads: • Output Transmit TOH Port Clock TOHTXCLK • Output Transmit TOH Port Address Latch Enable TOHTXALE • Output Transmit TOH Port Address TOHTXADDR • ...
Page 130
... The Transmit DCC ports are constant bit-rate ports that provide a possible source for either the RS or the MS DCC bytes in the outgoing STM-4 or the four STM-1 frames. In STM-4 mode, only the first DCC Port is active. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Figure Table 34) ...
Page 131
... The Transmit DCC Port consists of following leads: • Inputs Transmit DCC Data DCCTXDATA1..4 • Outputs Transmit DCC Clock DCCTXCLK1..4 The index indicates the port, one per transmit line. The Transmit DCC Clocks DCCTXCLK1..4 have a constant frequency and depend on the configured mode, as indicated in following table: ...
Page 132
... Transmit Line Ring Port / Alarm Interface of the source and the external source mode has to be selected (ExternalSourceSelect asserted). Figure 38 shows the use of the external Line Alarm Indication (Ring) Port Interface. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Table 37). The Receive DCC port has to be enabled by the ...
Page 133
... Output Receive Line Alarm Indication (Ring) Port data LRPRXDATA The Transmit Line Alarm Indication (Ring) Port Interface consists of following leads: • Input Transmit Line Alarm Indication (Ring) Port clock LRPTXCLK • Input Transmit Line Alarm Indication (Ring) Port frame sync LRPTXFS • ...
Page 134
... Note the address corresponding to the master VC is used for concatenated structures. E.g., when mapping four VC-4/STS-3c’s SPE in a STM-4/OC-12, only 0x0, 0x3, 0x6 and 0x9 will be valid values for A[7:4]. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 High Order path number A3 A2 ...
Page 135
... POH port interface, while the B3 BIP-8 can be used as error mask on the calculated BIP-8 for test purposes. The Transmit POH Port consists of following leads: • Output Transmit POH Port Clock POHTXCLK • Output Transmit POH Port Address Latch Enable POHTXALE • Output Transmit POH Port Address POHTXADDR • ...
Page 136
... The Transmit High Order Alarm Indication (Ring) Port Interface leads must then be connected to VSS. Figure 39 shows the use of the internal High Order Alarm Indication (Ring) Port Interface. Figure 39. Internal High Order Alarm Indication (Ring) Port Interface PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Tx High Order Path POH Generator ...
Page 137
... Output Receive High Order Alarm Indication (Ring) Port data PRPRXDATA The Transmit High Order Alarm Indication (Ring) Port Interface consists of following leads: • Input Transmit High Order Alarm Indication (Ring) Port clock PRPTXCLK • Input Transmit High Order Alarm Indication (Ring) Port frame sync PRPTXFS • ...
Page 138
... Per ATM Stream Settings • Enable/disable demapping (shared with egress PPP) • Cell delineation • Threshold for leaving SYNC-state = ALPHA ( 15) • Threshold for entering SYNC-state = DELTA ( 15) • Enable/disable transition from Correction- to Detection-state while in SYNC: when PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - ...
Page 139
... Rx FIFO (shared with egress PPP) 24 -1) discarded due to cell filtering (discards due to HEC errors 16 -1) with corrected HEC error 16 -1) with uncorrected HEC error 16 -1) discarded due to Rx FIFO overflow PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
Page 140
... UTOPIA interface block. When mapping into a certain SDH/SONET stream is disabled, software has to configure the POH Generator to insert the UNEQUIPPED activation pattern in the corresponding path. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 24 -1) received from Tx FIFO (shared with ingress PPP) ...
Page 141
... VC-3/STS-1, corresponding to 12 PHY’s The PHAST-12P does not support Async-Control-Character-Map (ACCM) handling. 1. PPP octet boundaries are aligned with SDH High Order VC/SONET STS-SPE byte boundaries PHAST-12P Device DATA SHEET TXC-06412B 1 mapping and demapping of HDLC-like PPP PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 142
... Enable/disable FCS stripping (don’t care in transparent mode) • FCS size ( bit) (don’t care in transparent mode) 11.13.1.3 Per PPP Stream Status & Alarms • FIFO Overflow: overflow occurred in Rx FIFO while a packet is being received (shared with egress ATM) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - ...
Page 143
... SOP and an EOP indication). Underflow error is not reported when it occurs in between packets (this means after an EOP indication but before the next SOP indication -1) forwarded towards Rx FIFO (shared with egress ATM) PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
Page 144
... Input write enable PPUTTXENB • Output cell available PPUTPTPACLAV(3-0) The maximum clock frequency is 50 MHz and the data and control signals are transferred on the rising edge of this clock. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - 24 -1) received from Tx FIFO (shared with ingress ATM) ...
Page 145
... Output start of cell PPUTRXSOPC • Input read enable PPUTRXENB • Output cell available PPUTPRPACLAV(3-0) The maximum clock frequency is 50 MHz and the data and control signals are transferred on the rising edge of this clock PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 146
... Input address PPUTTXADDR(4-0) • Input data PPUTTXDATA(15-0) • Input parity PPUTTXPRTY • Input start of packet PPUTTXSOPC • Input end of packet PPUTTXEOP • Input word modulo PPTXMOD • Input error PPTXERR • Input write enable PPUTTXENB PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - ...
Page 147
... Per CLAV Setting • Timeslot for direct status (shared with Tx UTOPIA) 11.15.1.4 Per POS-PHY Port Status & Alarms • SOP-EOP error • Parity error (shared with Tx UTOPIA) • Overflow error (shared with Tx UTOPIA PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 148
... CLAV signal. This value must always be larger than 0. Not that setting this value to X means that once the reading of a packet from the FIFO is started, at least X number of words can be read (shared with Rx UTOPIA) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - ...
Page 149
... BIP-96 in STM-4/OC-12 mode, B2 BIP-24 in STM-1/OC-3 mode) and path (B3 BIP-8). The assumed distribution of errors needs to be configured: PoissonErrorCheck 0 (Default PHAST-12P TOH Monitor TOH Generator Description Bursty distribution of errors is assumed (SDH). Poisson distribution of errors is assumed (SONET). PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
Page 150
... T. The value of time base T can be set to 500 EXC_Use125usCounter configuration. The excessive signal defect (dEXC) is declared if the accumulated BIP error count since the start of the detection interval is greater than or equal to EXC_DetectionErrorThreshold errors. The interval duration is EXC_DetectionWindowSize * T. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - s or 125 s via the ...
Page 151
... The following TTI message types are supported Repeating non-specific byte J0 Repeating specific byte 16-byte trace message Repeating non-specific byte J1 16-byte trace message 64-byte trace message with TFAS 64-byte trace message with CR/LF PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 152
... SDH/SONET Related Performance Counters The PHAST-12P supports the following SDH/SONET related performance counters: • RS/section counters per line interface: • B1 error count, configurable to count either BIP errors or errored frames 1. A multiframe frames, depending on the TTI format. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 - 1 . The TIM defect is ...
Page 153
... Number of cells discard due to FIFO overflow • Number of cells with corrected HEC error • Number of cells with uncorrected HEC error • ATM mapping: • Number of good cells received from the FIFO PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 154
... The one second boundary is generated by the internal one second clock which is either derived from the PHAST-12P system clock or from the external REFONESECCLK input lead. The performance counters can be reset by writing 0x91 into the ResetCounters register. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Description Clear-on-read mechanism: the counters are copied to the shadow registers and cleared upon a read access ...
Page 155
... INT/IRQ output lead used to indicate a logical ‘ Defect_Latch not Defect_Mask i AND ( Summary not Summary_Mask i AND not General_Mask i AND OR not APS_Mask ) k AND k ( HINT HINTEN ) AND ’ number of logical expressions ( PHAST-12P Device DATA SHEET TXC-06412B ) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 156
... OR & = AND ~ = NOT index ranges range #VCs range #lines) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 MicroProcessor Interrupt (HINT & HINTEN) xor ~MPINTLEVEL General Interrupt APS Interrupt Figure 41 ...
Page 157
... Figure 42. High Order Point Tracker Retimer Interrupt Tree PHAST-12P Device CorrDefects_Summary.DetectedConcat_Event & ~CorrDefects_SummaryMask.DetectedConcatEvent DetectedConcat_Event_LatchedForInt & ~DetectedConcat_Event_Mask CorrDefects_Summary.Summary[ho] & ~CorrDefects_SummaryMask.Summary[ho] VCx[ho].CorrDefects_LatchForInt.AIS & ~VCx[ho].CorrDefects_Mask.AIS VCx[ho].CorrDefects_LatchForInt.LOP & ~VCx[ho].CorrDefects_Mask.LOP VCx[ho].CorrDefects_LatchForInt.Fifo_Error & ~VCx[ho].CorrDefects_Mask.Fifo_Error PRELIMINARY TXC-06412B-MB, Ed. 2 DATA SHEET TXC-06412B June 2005 ...
Page 158
... PHAST-12P Device DATA SHEET High Order Pointer Tracking, Retiming and Pointer Generation TXC-06412B - POH Monitor Interrupt PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Common_Status.Summary_latchedForInt[ho] & Common_Config.Summary_Mask[ho] VC_Status[ho].CorrDefects_LatchedForInt.SSF & ~VC_Config{ho}.CorrDefects_Mask.SSF VC_Status[ho].CorrDefects_LatchedForInt.TIM & ~VC_Config{ho}.CorrDefects_Mask.TIM VC_Status[ho].CorrDefects_LatchedForInt.TTIZERO & ~VC_Config{ho}.CorrDefects_Mask.TTIZERO VC_Status[ho].CorrDefects_LatchedForInt.DEG & ...
Page 159
... CorrDefects_LatchForInt.TIM & ~CorrDefects_Mask.TIM CorrDefects_LatchForInt.MSOHM_CI_SSF & ~CorrDefects_Mask.MSOHM_CI_SSF CorrDefects_LatchForInt.DEG & ~CorrDefects_Mask.DEG CorrDefects_LatchForInt.EXC & ~CorrDefects_Mask.EXC CorrDefects_LatchForInt.RDI & ~CorrDefects_Mask.RDI CorrDefects_LatchForInt.AIS & ~CorrDefects_Mask.AIS CorrDefects_LatchForInt.SF & ~CorrDefects_Mask.SF CorrDefects_LatchForInt.K1K2_Event & ~CorrDefects_Mask.K1K2_Event CorrDefects_LatchForInt.S1_Event & ~CorrDefects_Mask.S1_Event APS_Defects_LatchForInt.DEG & ~APS_Defects_Mask.DEG APS_Defects_LatchForInt.SF & ~APS_Defects_Mask.SF APS_Defects_LatchForInt.K1K2_Event & ~APS_Defects_Mask.K1K2_Event PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 160
... PHAST-12P Device DATA SHEET High Order Pointer Tracking, Retiming and Pointer Generation TXC-06412B - APS Interrupt PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 APS_Interrupts(APS Pointer Tracker/Retimer) & ~ APS_Interrupts_Mask(APS Pointer Tracker/Retimer) Higher Order Pointer Tracker/Retimer Interrupt (APS) APS_Interrupts(Receive APS) & ~ APS_Interrupts_Mask(Receive APS) CorrDefects_LatchForInt.OOF & ~ CorrDefects_Mask.OOF CorrDefects_LatchForInt.LOF & ...
Page 161
... APS_Interrupts_Mask(TOH Monitor APS Line 3) TOH Monitor APS Interrupt (TOH Monitor Line 3) APS_Interrupts(TOH Monitor APS Line 4) & ~ APS_Interrupts_Mask(TOH Monitor APS Line 4) TOH Monitor APS Interrupt (TOH Monitor Line 4) Figure 46. APS Interrupt Tree (part 2) PHAST-12P Device DATA SHEET TXC-06412B PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 162
... PHAST-12P Device DATA SHEET High Order Pointer Tracking, Retiming and Pointer Generation TXC-06412B - General Interrupt Figure 47. General Interrupt Tree (part 1) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 GeneralInterrupts(Global Control) & ~ GeneralInterrupts_Mask(Global Control) GlobalControlSummary_LatchForInt(System LOC) & ~ GlobalControlSummary_Mask(System LOC) GlobalControlSummary_LatchedForInt(Rx Line 1 LOC) & ~ GlobalControlSummary_Mask(Rx Line 1 LOC) GlobalControlSummary_LatchedForInt(Rx Line 2 LOC) & ...
Page 163
... POH Monitor Interrupt (Terminal Side) GeneralInterrupts(Line Pointer Tracker/Retimer) & ~ GeneralInterrupts_Mask(Line Pointer Tracker/Retimer) Higher Order Pointer Tracker/Retimer Interrupt (Line Side) GeneralInterrupts(TOH Ring Port) & ~ GeneralInterrupts_Mask(TOH Ring Port) CorrDefects_LatchForInt.CRC_Error & ~ CorrDefects_Mask.CRC_Error CorrDefects_LatchForInt.LOC & ~ CorrDefects_Mask.LOC PRELIMINARY TXC-06412B-MB, Ed. 2 PHAST-12P Device DATA SHEET TXC-06412B June 2005 ...
Page 164
... PHAST-12P Device DATA SHEET High Order Pointer Tracking, Retiming and Pointer Generation TXC-06412B - Figure 49. General Interrupt Tree (part 3) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 GeneralInterrupts(Receive TOH/DCC Port) & ~ GeneralInterrupts_Mask(Receive TOH/DCC Port) TOH_Events_Summary[9][4] & ~ TOH_Events_Summary_Mask[9][4] TOH_Events_LatchForInt[9][36] & ~ TOH_Events_Mask[9][36] GeneralInterrupts(TOH Monitor Line 1) & ~ GeneralInterrupts_Mask(TOH Monitor Line 1) TOH Monitor General Interrupt (Line 1) GeneralInterrupts(TOH Monitor Line 2) & ...
Page 165
... The BYPASS test instruction (111) provides the ability to bypass the PHAST- 12P boundary scan and instruction registers Figure 50, one cell of a boundary scan register is assigned to each input Figure 22. PHAST-12P Device DATA SHEET TXC-06412B Figure 50. Figure 50. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 166
... Boundary Scan Chain A boundary scan description language (BSDL) source file is available via the Products page of the TranSwitch Internet World Wide Web site at www.transwitch.com. PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Boundary Scan Register CORE LOGIC ...
Page 167
... PHAST-12P Device DATA SHEET TXC-06412B ESCRIPTIONS 170.) (See page 174.) (See page 189.) (See page 189.) (See page 201.) (See page 210.) (See page 212.) 214.) 214.) 214.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 168
... LocDivider 0x0020 LocEntryThreshold 0x0024 LocExitThreshold 0x0028 0 External1secRef_Select 0x002C 0 DeviceInitialized 0x0030 GP_Input PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_GLOBAL_CONTROL) Init Access ro T_DeviceIdentification Device identification. 0x0 rw STM-4/OC-12 Mode when 0x1: Line 622.08 Mbit/s signal, lines are not used. STM-1/OC-3 Mode when 0x0: lines are 155 ...
Page 169
... Version or revision level. The initial version will be 0x0. The version register will be incremented with each new revision of the part. 0x0 Indicates the Mask Level. 0x0 Indicates the Growth Field. 0x0 Reserved. PHAST-12P Device DATA SHEET TXC-06412B Description Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 170
... RESETH 0x0002 Reserved 0x0004 Reserved 0x0006 Reserved 0x0008 RxLine1_Reset PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOH_RING_PORT) Init Access All 0x0 rw Array (4) of boolean Offset between two elements = 0x2. Array index indicates the line (= line number - 1). ...
Page 171
... Interrupt and performance configuration. 0x0 ro Global device interrupt (HINT = Hardware INTerrupt). 0x0 rw The global device interrupt is enabled when 0x1, no interrupt will be generated when 0x0 (HINTEN = Hardware INTerrupt ENable). PHAST-12P Device DATA SHEET TXC-06412B Description Description (See page 172.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 172
... GeneralInterrupts_Mask Table 8: Interrupt Configuration Offset Bits Name 0x0000 ResetCounters LatchForIntCtrl 10 Reserved PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 7: Interrupt (T_INTERRUPT) Init Access 0x0 ro General Interrupts Register: • bit 0: Global Control Interrupt • bit 1: Pointer Generator • bit 2: Reserved • ...
Page 173
... Register that contains the values for Tx K1 and Tx K2 located in MSB located in LSB. 0x0 Register that contains the values for Status and Request. Status is located in MSB, Request is located in LSB. PHAST-12P Device DATA SHEET TXC-06412B Description (See page 173.) (See page 173.) Description (T_TX_APS_Config) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 174
... CorrDefects_Unlatched 0x0080 CorrDefects_LatchForInt 0x00C0 DirectStatus_Config 0x00D0 Common_Config 0x00D8 CorrDefects_Summary 0x00DC CorrDefects_SummaryMask 0x00E0 PHY_Port_Config PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_DI_UTOPIA_POSPHY) Init Access rw Array (12) of T_DIUP_CorrDefects Offset between two elements = 0x2. Array index indicates the PHY. Defects mask. ro Array (12) of T_DIUP_CorrDefects Offset between two elements = 0x2 ...
Page 175
... The parity is calculated over databus only when 0x1, over databus and control signals when 0x0. Applies to both UTOPIA and POS-PHY mode. 0x0 Range 0 to 124 Threshold used for low transition of STPA. Applies to POS-PHY mode only. PHAST-12P Device DATA SHEET TXC-06412B (T_DIUP_CorrDefects) Description Description (T_DI_UTOPIA_POSPHY_Common_Config) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 176
... Table 18: POH Generator Common Configuration Offset Bits Name 0x0000 Config_Channel 0x0002 AUG1_Mode_Config PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x1B Range 0 to 124 Maximum number of free words which may be available in the FIFO before the near full indication (PTPA low) is set on the POS-PHY interface ...
Page 177
... Reserved. Init T_VCXPG_RAMBytes Configuration of the POH RAM bytes. T_VCXPG_Mode_record Mode Configuration. T_VCXPG_Control_record Source selection for the POH bytes. PHAST-12P Device DATA SHEET TXC-06412B Description (T_VCXPG_VC_Config) Description (See page 178.) (See page 178.) (See page 179.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 178
... Force_Uneq 2 Force_SupUneq 3 UniDirectional 4 OneBitRDI 5 Reserved PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_VCXPG_RAMBytes) Init All 0x0 Array (64) of byte Offset between two elements = 0x2. Array index indicates the TTI byte number. TTI-message for insertion in the J1 location. • bytes 0-15 for 16 byte TTI message • ...
Page 179
... VCXPG_RAM = Use RAM as source • VCXPG_POH_INTF = Use POH Port Interface as source 0x0 0x0 = VCXPG_RAM 0x1 = VCXPG_POH_INTF Selects the source of the N1 Byte. • VCXPG_RAM = Use RAM as source • VCXPG_POH_INTF = Use POH Port Interface as source PHAST-12P Device DATA SHEET TXC-06412B Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 180
... B2_BIP_BitErrors_MSB 0x0006 B2_BIP_BlockErrors 0x0008 REI_BIP_Errors 0x000A DefectSeconds 0 NearEndDefectSec 1 FarEndDefectSec PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 24: TOH Monitor (T_TOH_MONITOR) Init Access All 0x0 rw Array (16) of byte Offset between two elements = 0x2. Array index indicates the TTI byte number. ...
Page 181
... Line AIS detected on K2. 0x1 Signal Fail. 0x1 New (debounced) K1K2 value accepted. 0x1 New (debounced) S1 value accepted. (T_TOH_MONITOR_APS_Defects) Init 0x1 Signal Degrade. 0x1 Signal Fail. 0x1 New K1K2 value accepted. PHAST-12P Device DATA SHEET TXC-06412B Description Description Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 182
... SSF_AIS_Insert_Disable 9 EXC_AIS_Insert_Disable 10 Framer_AIS_Force 11 RSOH_AIS_Force 12 MSOH_AIS_Force PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOH_MONITOR_Common_Config) Init 0x0 B1 BER performance counter reports bit errors when 0x1, block errors when 0x0. 0x0 REI BIP performance counter reports bit errors when 0x1, block counter when 0x0 ...
Page 183
... Allowed number of bit errors within a window for DEG recovery (error threshold for which the DEG state will not be exited). 0x1 Range 1 to 65535 Window size for DEG recovery in 125/500 us intervals. PHAST-12P Device DATA SHEET TXC-06412B Description Description (See page 183.) (See page 184.) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 184
... DEG_RecoveryErrorThreshold _LSB 0x0006 Recovery_Config DEG_RecoveryWindowSize DEG_RecoveryErrorThreshold _MSB PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_BIP_PoissonDetector_Config) Init 0xFFFF Range 1 to 65535 Minimum number of bit errors within a window for EXC detection. 0xFFFF Range 1 to 65535 Window size for EXC detection in 125/500 us intervals. ...
Page 185
... EXORed with the calculated BIP. These locations must be 0x00 for normal operation. Note 4: A1 bytes (bytes 0-11) are initialized to 0xF6, A2 bytes (bytes 12- 23) are initialized to 0x28. All other entries are initialized to 0x00. PHAST-12P Device DATA SHEET TXC-06412B Description (See page 186.) (See page 186.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 186
... K1K2_Source RDI_Source 0x0002 K1K2_Value 0x0004 RDI_Value 0x0006 0 Scrambling_Disable PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOHG_Common_Config) Init 0x0 Enables TX side TOH port when 0x1. (T_TOHG_Line_Config) Init 0x0 Select mode for DCC port. The DCC port requests RS DCC bytes (D1-D3) when 0x1 and MS DCC bytes (D4-D12) when 0x0 ...
Page 187
... STM-1 mode = line number (1-4). • bit position ( least significant bit is 0) See also [ITU-T G.707/Y.1322] for the TOH bytes locations. PHAST-12P Device DATA SHEET TXC-06412B Description (See page 189.) (See page 189.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 188
... Table 37: Receive TOH and DCC Port Offset Bits Name 0x02C0 TOH_Events_Summary_Mask 0x0300 TOH_Events_LatchForInt 0x0400 TOH_Contents PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_RX_TOH_DCC_PORT) Init Access All 0x1 rw Array (4) of nine_bits Offset between two elements = 0x2. Array index indicates the summary of nine TOH_Events_LatchedForInt bits ...
Page 189
... Offset between two elements = 0x20. Array index indicates the high order path. Configuration and status. PHAST-12P Device DATA SHEET TXC-06412B Description Description Description (See page 190.) (See page 190.) (See page 190.) (See page 177.) (See page 190.) PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 190
... CorrDefects_LatchForInt 0x0012 Reserved 0x0014 Reserved 0x0016 Reserved PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0xFFF Defects summary, one bit per high order path. Least significant bit corresponds to the first high order path. 0x1 Event telling detected concatenation has changed. ...
Page 191
... Positive Justifications as generated by the Pointer Generator. 0x0 Range 0 to 0xFE Negative Justifications as generated by the Pointer Generator. Init 0x1 AIS, detected by the Pointer Tracker. 0x1 Loss of Pointer. 0x1 Retimer FIFO Error. PHAST-12P Device DATA SHEET TXC-06412B (T_HOPTRRT_VC3_TUG3_Config) Description Description Description (T_HOPTRRT_Defects) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 192
... Table 49: POS/ATM Demapper Per PHY Offset Bits Name 0x0000 CorrDefects_Unlatched 0x0002 CorrDefects_LatchForInt 0x0004 CorrDefects_Mask 0x0006 PerfCounters_Shadow PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_POS_ATM_DEMAPPER) Init Access Array (12) of T_DMP_DefectsAndCounters page 192.) Offset between two elements = 0x20. Array index indicates the PHY. ...
Page 193
... Number of frames longer than the maximum frame length. Applies to PPP (no transparent) mode only. 0x0 Number of frames shorter than the minimum frame length. Applies to PPP (no transparent) mode only. PHAST-12P Device DATA SHEET TXC-06412B (T_DMP_Defects) Description (T_DMP_PerfCounters) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 194
... Phy_Enable 1 Descrambling_Disable 0x0002 Thresholds Alpha Delta PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x0 One second performance monitoring mechanism is enabled when 0x1, otherwise clear-on-read performance monitoring mechanism is enabled. Applies to both ATM and PPP modes. 0x4 Loss of Cell Delineation (LCD) integration time in ms. ...
Page 195
... Applies to ATM mode only. 0x0 Reserved. 0x0 The CLP field for the match header mask. Applies to ATM mode only. 0x0 The PTI field for the match header mask. Applies to ATM mode only. PHAST-12P Device DATA SHEET TXC-06412B (T_DMP_Phy_Config) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 196
... CorrDefects_Mask 0x0240 Common_Config 0x0280 IngressFIFO_Reset 0x02A0 AUG1_Mode_Config PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x0 Enables transparent mode when 0x1. In transparent mode the HDLC functionality is bypassed, i.e., all bytes are passed through transparently (no framing, no byte destuffing, no abort detection, no FCS processing) ...
Page 197
... Number of packets for which the error signal on the POS-PHY Level 2 interface was asserted during the last word transfer of that packet. Applies to PPP mode only. PHAST-12P Device DATA SHEET TXC-06412B Description (See page 198.) (T_MAP_PerfCounters) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 198
... HEC_IdleUnas_Enable 0x0004 HEC_Manip HEC_CorruptionMask_XO HEC_Manipulation 0x0006 HeaderPattern_GFC_VPI PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x0 One second performance monitoring mechanism is enabled when 0x1, otherwise clear-on-read performance monitoring mechanism is enabled. Applies to both ATM and PPP mode. 0x1B Range 1 to 128 The minimum number of words which has to be available in the FIFO before the POS/ATM Mapper starts to read data from that FIFO ...
Page 199
... Applies to PPP (no transparent) mode only. 0x0 If transparent mode is enabled: Byte to be inserted as payload 1) during Tx FIFO underflow if mapping is enabled mapping is disabled. Applies to PPP (transparent) mode only. PHAST-12P Device DATA SHEET TXC-06412B (T_MAP_Phy_Config) Description PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 ...
Page 200
... Bits Name 0x0000 0 PointerZero 0x0002 0 Reserved 0x0004 0 ExtFramePulseExpected 0x0006 0 ExtFramePulseNegEdge 0x0008 ExtFramePulseOffset 0x000A Reserved 0x000C Reserved PRELIMINARY TXC-06412B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 58: Pointer Generator (T_RETIMER) Init Access rw T_AUG1_Mode_Config AUG-1 mode configuration. rw T_RT_Defects Correlated defects mask. ro T_RT_Defects Correlated defects ...