M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet

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M25P10-AVMN6TP

Manufacturer Part Number
M25P10-AVMN6TP
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of M25P10-AVMN6TP

Lead Free Status / Rohs Status
Compliant

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FEATURES SUMMARY
ENHANCED VERSION OF THE M25P10
This device is an enhanced version of the
M25P10. The enhanced features include: larger
page size, shorter programming time, higher clock
frequency.
November 2003
1 Mbit of Flash Memory
Page Program (up to 256 Bytes) in 1.4ms
(typical)
Sector Erase (256 Kbit) in 0.8s (typical)
Bulk Erase (1 Mbit) in 2.5s (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
40MHz Clock Rate (maximum)
Deep Power-down Mode 1 A (typical)
Electronic Signature (10h)
More than 100,000 Erase/Program Cycles per
Sector
More than 20 Year Data Retention
1 Mbit, Low Voltage, Serial Flash Memory
With 40 MHz SPI Bus Interface
Figure 1. Packages
VDFPN8 (MP)
150 mil width
8
SO8 (MN)
(MLP8)
1
M25P10-A
1/38

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M25P10-AVMN6TP Summary of contents

Page 1

... More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention ENHANCED VERSION OF THE M25P10 This device is an enhanced version of the M25P10. The enhanced features include: larger page size, shorter programming time, higher clock frequency. November 2003 1 Mbit, Low Voltage, Serial Flash Memory With 40 MHz SPI Bus Interface Figure 1 ...

Page 2

... M25P10-A TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ENHANCED VERSION OF THE M25P10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SO and VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect ( SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 ...

Page 3

... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence Release from Deep Power-down and Read Electronic Signature (RES Figure 19. Release from Deep Power-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . 24 POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 20. Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 INITIAL DELIVERY STATE MAXIMUM RATING M25P10-A 3/38 ...

Page 4

... M25P10-A Table 8. Absolute Maximum Ratings AND AC PARAMETERS Table 9. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. AC Measurement Conditions Figure 21. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Capacitance Table 12. DC Characteristics Table 13. AC Characteristics (25MHz Operation Table 14. AC Characteristics (40MHz Operation, upon request - contact nearest ST sales office) 30 Figure 22. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 23 ...

Page 5

... SUMMARY DESCRIPTION The M25P10 Mbit (128K x 8) Serial Flash Memory, with advanced write protection mecha- nisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each con- taining 128 pages ...

Page 6

... M25P10-A SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be pro- grammed ...

Page 7

... Figure 5, is the clock polarity when the bus mas- ter is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= SPI Memory SPI Memory Device Device HOLD W M25P10 SPI Memory Device S HOLD W HOLD AI03746D MSB AI01438B 7/38 ...

Page 8

... M25P10-A OPERATING FEATURES Page Programming To program one data byte, two instructions are re- quired: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which con- sists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) ...

Page 9

... The environments where non-volatile memory de- vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P10-A boasts the following data protection mechanisms: Power-On Reset and an internal timer (t can provide protection against inadvertant changes while the power supply is outside the operating specification ...

Page 10

... M25P10-A Hold Condition The Hold (HOLD) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low ...

Page 11

... Table 3. Memory Organization Sector High Voltage Generator I/O Shift Register 256 Byte Data Buffer 18000h 10000h 08000h 00000h 256 Bytes (Page Size) X Decoder M25P10-A Address Range 18000h 1FFFFh 10000h 17FFFh 08000h 0FFFFh 00000h 07FFFh Status Register 1FFFFh Size of the read-only memory area 000FFh ...

Page 12

... M25P10-A INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...

Page 13

... Chip Select (S) High Instruction High Impedance – Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction com- pletion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion M25P10-A AI03750D 13/38 ...

Page 14

... M25P10-A Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence Instruction D High Impedance Q Read Status Register (RDSR) The Read Status Register (RDSR) instruction al- lows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress ...

Page 15

... Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not execut- ed once the Hardware Protected Mode (HPM) is entered AI02282D ) is initiated. While the Write W M25P10-A 15/38 ...

Page 16

... M25P10-A Table 6. Protection Modes W SRWD Mode Signal Bit Software Protected (SPM Hardware 0 1 Protected (HPM) Note defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summa- rized in Table 6. When the Status Register Write Disable (SRWD) ...

Page 17

... Chip Select (S) High. Chip Select (S) can be driven High at any time during data out- put. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress Data Out 1 Data Out MSB AI03748D M25P10-A 17/38 ...

Page 18

... M25P10-A Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Instruction D High Impedance Dummy Byte Note: 1. Address bits A23 to A17 are Don’t Care. Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data ...

Page 19

... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see Table 3 and Table 2) is not executed Data Byte MSB Data Byte 256 MSB AI04082B M25P10 19/38 ...

Page 20

... M25P10-A Figure 15. Sector Erase (SE) Instruction Sequence Note: 1. Address bits A23 to A17 are Don’t Care. Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decod- ed, the device sets the Write Enable Latch (WEL) ...

Page 21

... Bulk Erase cycle, and is 0 when it is com- pleted. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. M25P10-A 21/38 ...

Page 22

... M25P10-A Figure 17. Deep Power-down (DP) Instruction Sequence Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con- sumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions ...

Page 23

... C Instruction D High Impedance Q Note: The value of the 8-bit Electronic Signature, for the M25P10-A, is 10h. Release from Deep Power-down and Read Electronic Signature (RES) Once the device has entered the Deep Power- down mode, all instructions are ignored except the Release from Deep Power-down and Read Elec- tronic Signature (RES) instruction ...

Page 24

... M25P10-A Figure 19. Release from Deep Power-down (RES) Instruction Sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruc- tion byte has been received by the device, but be- fore the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Fig- ure 19), still insures that the device is put into Stand-by Power mode ...

Page 25

... V (min) level has elapsed, after V VSL (min), the device can be selected for CC delay is not yet PUW feed. Each device CC rail decoupled by CC drops from the CC , all operations are disabled and the WI Device fully accessible time M25P10-A has risen CC AI04009C 25/38 ...

Page 26

... M25P10-A Table 7. Power-Up Timing and V Symbol 1 V (min low t CC VSL 1 Time delay to Write instruction t PUW 1 Write Inhibit Voltage V WI Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains ...

Page 27

... Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 ® 7191395 specifiication for lead-free soldering processes , R2=500 ) Min. Max. –65 150 2 SO 260 2 VDFPN 260 –0.6 4.0 –0.6 4.0 3 –2000 2000 M25P10-A Unit °C ° 27/38 ...

Page 28

... M25P10-A DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 9. Operating Conditions Symbol V Supply Voltage ...

Page 29

... Test conditions specified in Table 9 and Table 10 Parameter 3 (peak to peak) 3 (peak to peak) Min 40MHz 20MHz – 0 –100 A V –0.2 CC Min. Typ. D.C. D. 0.1 0 100 M25P10-A Max. Unit ± 2 µA ± 2 µA 50 µA 5 µ Max. Unit 25 MHz 20 MHz ns ns V/ns V/ ...

Page 30

... M25P10-A Symbol Alt Output Disable Time t DIS SHQZ t t Clock Low to Output Valid CLQV Output Hold Time CLQX HO t HOLD Setup Time (relative to C) HLCH t HOLD Hold Time (relative to C) CHHH t HOLD Setup Time (relative to C) HHCH t HOLD Hold Time (relative to C) ...

Page 31

... Bulk Erase Cycle Time BE Note must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. Test conditions specified in Table 9 and Table 10 Parameter C M25P10-A Min. Typ. Max. Unit ...

Page 32

... M25P10-A Figure 22. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q 32/38 tSLCH tCHDX tCLCH MSB IN tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 ...

Page 33

... Figure 24. Hold Timing HOLD Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tHLCH tCHHL tCHHH tHLQZ tCH tCLQV M25P10-A tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449D 33/38 ...

Page 34

... M25P10-A PACKAGE MECHANICAL Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline SO-a Note: Drawing is not to scale. Table 15. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data Symb. Typ 1. 34/ Min. ...

Page 35

... M25P10 VDFPN-01 inches Min. Max. 0.0394 0.0000 0.0020 0.0138 0.0189 0.1260 0.1417 0.1496 0.1654 0.0197 0.0295 12° 35/38 ...

Page 36

... Standard SnPb plating Pb-Free, RoHS compliant Green package Note: 1. Available for SO8 package only 2. Available for MLP package only For a list of available options (speed, package, etc.) or for further information on any aspect of this 36/38 M25P10 device, please contact your nearest ST Sales Of- fice ...

Page 37

... Erroneous address ranges corrected in Memory Organisation table Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. 40MHz AC Characteristics table included as well as 25MHz. I 24-Nov-2003 2.0 values improved. Change of naming for VDFPN8 package Description of Revision (max), t CC3 M25P10-A (typ) and t (typ 37/38 ...

Page 38

... M25P10-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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