CY7B9234-270JC Cypress Semiconductor Corp, CY7B9234-270JC Datasheet

CY7B9234-270JC

Manufacturer Part Number
CY7B9234-270JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7B9234-270JC

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Cypress Semiconductor Corporation
Document #: 38-02014 Rev. *A
Features
Functional Description
The
CY7B9334 SMPTE HOTLink Receiver bolt on to the SMPTE
Scrambler
• SMPTE-259M-CD compliant along with SMPTE-259M
• Fibre Channel compliant
• DVB-ASI compliant
• RX PLL tolerant of long run length data patterns (>20
• 8B/10B-coded or 10-bit unencoded
• TTL synchronous I/O
• No external PLL components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
• Built-In Self-Test
• Single +5V supply
• 28-pin PLCC
• 0.8µ BiCMOS
encoder (CY7C9235) and decoder (CY7C9335)
bits)
twisted pair media
CY7B9234 Transmitter Logic Block Diagram
CY7B9234
BISTEN
MODE
CKW
Controller
RP
GENERATOR
CLOCK
LOGIC
ENN
TEST
SMPTE
ENA
(CY7C9235)
HOTLink
(D
D
b − h
0− 7
INPUT REGISTER
ENABLE
ENCODER
SHIFTER
)
SC/D (D
®
SVS(D
a
)
Transmitter
j
)
and
SMPTE HOTLink
FOTO
3901 North First Street
OUTA
OUTB
OUTC
SMPTE
and
INB (INB+)
SI(INB− )
REFCLK
Descrambler/Framer Controller (CY7C9335) completing the
four piece chipset to transfer uncompressed SMPTE-259M
encoded video over high-speed serial links (fiber, coax, and
twisted pair). SMPTE HOTLink supports SMPTE-259M-CD
standard data rates at 270 and 360 Mbps. Figure 1 illustrates
typical connections to host systems or controllers.
Eight or ten bits of user data or protocol information are loaded
into the SMPTE HOTLink transmitter and, in DVB mode, are
encoded. Serial data is shifted out of the three differential
positive ECL (PECL) serial ports at the bit rate (which is 10
times the byte rate).
The SMPTE HOTLink receiver accepts the serial bit stream at
its differential line receiver inputs and, using a completely
integrated PLL Clock Synchronizer, recovers the timing infor-
mation necessary for data reconstruction. The bit stream is
deserialized, and in DVB mode, decoded and checked for
transmission errors. Recovered bytes are presented in parallel
to the receiving host along with a byte rate clock.
The 8B/10B encoder/decoder can be disabled in SMPTE or
DVB systems that already encode or scramble the transmitted
data. I/O signals are available to create a seamless interface
with both asynchronous FIFOs (i.e., CY7C42X) and clocked
FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator
and checker allows testing of the transmitter, receiver, and the
connecting link as a part of a system diagnostic check.
SMPTE HOTLink devices are ideal for a variety of video appli-
cations including video transmission equipment, video
recorders, video editing equipment, and video routers.
CY7B9334 Receiver Logic Block Diagram
BISTEN
MODE
INA+
INA−
A/B
SO
RF
LOGIC
TEST
PECL
TTL
San Jose
®
CLOCK
SYNC
Transmitter/Receiver
CKR
,
CA 95134
DATA
RDY
(Q
DECODER
REGISTER
DECODER
REGISTER
FRAMER
SHIFTER
OUTPUT
Q
b − h
0− 7
Revised April 27, 2004
)
SC/D (Q
CY7B9234
CY7B9334
408-943-2600
a
RVS(Q
)
j
)
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CY7B9234-270JC Summary of contents

Page 1

... Single +5V supply • 28-pin PLCC • 0.8µ BiCMOS Functional Description ® The CY7B9234 SMPTE HOTLink CY7B9334 SMPTE HOTLink Receiver bolt on to the SMPTE Scrambler Controller (CY7C9235) CY7B9234 Transmitter Logic Block Diagram SC 0− − SVS(D RP ENN ENA ENABLE INPUT REGISTER ...

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... HOST Figure 1. SMPTE HOTLink System Connections CY7B9234 Transmitter Pin Configuration PLCC Top View 2726 BISTEN 25 5 GND 24 6 MODE 23 7 7B9234 CCQ SVS 1213 1718 h 7 Pin Description CY7B9234 SMPTE HOTLink Transmitter Name I/O Description D TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW 0− ...

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... Pin Description CY7B9234 SMPTE HOTLink Transmitter (continued) Name I/O Description ENN TTL In Enable Next Parallel Data. If ENN is LOW, the data appearing on D CKW is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D next rising edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space between user data ...

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... INB± pair may be used as a differential serial data input. directly. When left floating (internal resistors hold the MODE pin at a−j or GND BISTEN has the same timing CY7B9234 CY7B9334 output. RVS has the j , registered shifter contents CC . 0−7 ...

Page 5

... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encoding. Test logic is discussed in more detail in the CY7B9234 SMPTE HOTLink Transmitter Operating Mode Description. CY7B9334 SMPTE HOTLink Receiver Block Diagram Description ...

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... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic for the decoder. Test logic is discussed in more detail in the CY7B9334 SMPTE HOTLink Receiver Operating Mode Description. CY7B9234 CY7B9334 − , SC/D, and 0 ...

Page 7

... Ambient Temperature with Power Applied..................................................−55°C to +125°C Supply Voltage to Ground Potential ................ −0.5V to +7.0V DC Input Voltage ................................................ −0.5V to +7.0V Output Current into TTL Outputs (LOW) ......................30 mA CY7B9234/CY7B9334 Electrical Characteristics Parameter Description TTL OUTs, CY7B9234: RP; CY7B9334 Output HIGH Voltage OHT V Output LOW Voltage OLT I ...

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... CY7B9234/CY7B9334 Electrical Characteristics Parameter Description Differential Line Receiver Input Pins: INA+, INA−, INB+, INB− V Input Differential Voltage DIFF |(IN+) − (IN−)| V Highest Input HIGH Voltage IHH V Lowest Input LOW Voltage ILL I Input HIGH Current IHH [4] I Input LOW Current ILL ...

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... CKW, but not RP function or timing pF. L −2.0V, over the operating range. CC /10 if data is being received. See note. CKW , SC/D, and RVS) are loaded with similar DC and AC loads. 0−7 , and V specification (approximately CY7B9234 CY7B9334 7B9234-270 7B9234-400 Min. Max Min. Max Unit −3 − − ...

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... Switching Waveforms for the CY7B9234 SMPTE HOTLink Transmitter CKW ENA NOTES 10,11 D – SC/D, SVS, BISTEN RP t CPWL CKW t SD ENN D – SC/D, SVS, BISTEN Document #: 38-02014 Rev CKW t CPWH t CPWL t SENP t t HENP SD VALID DATA PDF t PDR t PPWH t CKW t CPWH ...

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... NOTE 20 SO Static Alignment t /2− ± INA , ± INB SAMPLE WINDOW Document #: 38-02014 Rev CKR t CPRL PRF t CKX t CPXH 1.5V Error-F ree Window t /2− ± INA ± INB BIT CENTER CY7B9234 CY7B9334 t ROH t EFW t B BIT CENTER Page [+] Feedback ...

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... Mbytes per second for -400 devices) over several types of serial interface media. Figure 2 illus- trates the flow of data through the SMPTE HOTLink CY7B9234 transmitter pipeline. Data is latched into the trans- mitter on the rising edge of CKW when enabled by ENA or ENN asserted LOW with a 60% LOW/40% HIGH duty cycle when ENA is LOW ...

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... Receiver interface to fiber-optic and copper media. More information on interfacing SMPTE HOTLink to various media can be found in the “HOTLink Design Considerations” appli- cation note. CY7B9234 SMPTE HOTLink Transmitter Operating Mode Description In normal operation, the Transmitter can operate in either of two modes. The Encoded mode allows a user to send and receive eight (8) bit data and control information without first converting it to transmission characters ...

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... Q ENR CKR 0 − ,SC/D ENN CKW 0 − 7 SMPTE HOTLink TRANSMITTER SMPTE HOTLink RECEIVER Q ,SC/D CKR 0 − CKW 0 − 8 Figure 5. Seamless FIFO Interface CY7B9234 CY7B9334 = 111 00000 and 7−0 CLOCKED FIFO 7C44X/ − ,SC/D 0 − 7 7B9234 7B9334 RDY Q ,SC/D 0 − ENW D 0 − 8 ...

Page 15

... K28.7 (C7.0). CC Transmitter Test Mode Description The CY7B9234 Transmitter offers two types of test mode operation, BIST mode and Test mode normal system application, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver, and the link connecting them ...

Page 16

... Termination .01UF VCC IB IB– IA IA– 82 .01UF Fiber-optic 8 20 PECL Load CY7B9234 CY7B9334 .01UF VCC Fiber-optic Fiber Tx TX TX+ TX– GND Coax or Twisted Pair A B 270 270 .01UF 649 1500 RL/2 Coax or Twisted Pair RL/2 Optional Signal Det. 270 .01UF ...

Page 17

... RVS output in the Receiver. This can be done by explicitly sending a violation with the SVS input, or allowing the trans- mitter BIST loop to run while the Receiver runs in normal mode. The BIST loop includes deliberate violation symbols and will adequately test the RVS function. CY7B9234 CY7B9334 OUTA OUTB OUTC ...

Page 18

... The only restrictions upon the data encoding method is that it contain suitable transition density for the Receiver PLL data synchro- nizer (one per 10 bit byte) and that it be compatible with the transmission media. CY7B9234 CY7B9334 ), a context control bit (SC/D), and a system 7 = 111 7− ...

Page 19

... Transmitter, the Receiver and the link connecting them. This mode is available with minimal impact on user system logic, and can be used as part of the normal system diagnostics. Typical connections and timing are shown in Figure 7. CY7B9234 CY7B9334 RVS SC/D Qouts Name 0 0 00− ...

Page 20

... F and f, G and g, and H and h. Bits i and j are derived, respectively, from (A,B,C,D,E) and (F,G,H). The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC-2 specification, B corresponds to bit 1, as shown below CY7B9234 CY7B9334 , 0-7 FC-2 45 Bits: 7654 3210 0100 0101 Page [+] Feedback ...

Page 21

... It is also negative at the end of the 6-bit sub-block if the 6-bit sub-block is 111000, and it is negative at the end of the 4-bit sub-block if the 4-bit sub-block is 1100. 3. Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. CY7B9234 CY7B9334 Page [+] Feedback ...

Page 22

... CY7B9234 CY7B9334 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 010 ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

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... CY7B9234 CY7B9334 Page [+] Feedback ...

Page 29

... CY7B9234 CY7B9334 Page [+] Feedback ...

Page 30

... Code Rule Violation and SVS Tx Pattern 111 00000 100111 1000 111 00001 001111 1010 111 00010 110000 0101 Running Disparity Violation Pattern 111 00100 110111 0101 CY7B9234 CY7B9334 Current RD+ abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 ...

Page 31

... Ordering Information Speed Ordering Code [33] 270 CY7B9234-270JC [33] 400 CY7B9234-400JC Speed Ordering Code Package Name [34] 270 CY7B9334-270JC [34] 400 CY7B9334-400JC Notes: 29. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special Character has the same effect as asserting SVS = HIGH. ...

Page 32

... Document History Page Document Title:CY7B9234/CY7B9334 SMPTE HOTLink Document Number: 38-02014 REV. ECN NO. Issue Date ** 105852 03/28/01 *A 282669 See ECN Document #: 38-02014 Rev. *A ® Transmitter/Receiver Orig. of Change Description of Change SZV Change from Spec number: 38-00629 to 38-02014 BCD Removed data rate 177 Mbps and the corressponding video standard ...

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