DG538ADJ Vishay, DG538ADJ Datasheet

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... CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a “T” configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to – MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up. For more information refer to Vishay Siliconix applications note AN502 V– ...

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... DG534A/538A Vishay Siliconix DG538ADJ Dual-In-Line 1 GND GND GND GND 8 Latch/Drivers Top View I Note b www.vishay.com V– GND 24 S GND GND A2 GND GND GND 8 Note c v 0.8 V Logic “0” 2.4 V Logic “1” Don’t Care DG538ADN PLCC GND 6 24 ...

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... V Logic “1” Don’t Care Package 20-Pin Plastic DIP DG534ADJ _ 20-Pin PLCC DG534ADN 20-Pin Sidebraze DG534AAP/883, 5962-906021MRC 28-Pin Plastic DIP DG538ADJ _ 28-Pin PLCC DG538ADN 28-Pin Sidebraze DG538AAP/883, 5962-8976001MXA DG534A/538A Vishay Siliconix On Switch Maintains previous state None (latches cleared) None S A1 ...

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... DG534A/538A Vishay Siliconix V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V– V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 mA, whichever occurs first mA, whichever occurs first Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Pulsed l ms 10% Duty . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Symbol Analog Switch g Analog Signal Range V ANALOG Drain-Source r DS(on) On-Resistance Resistance Match Dr DS(on) Between Channels ...

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... Room Full Full Full Functional Test Only Full Full Room Full Room Full Room Full See Figure 1 Room Full Room Room Room DG534A/538A Vishay Siliconix A Suffix D Suffix –55 to 125_C –40 to 85_C Typ Min Max Min Max –75 –65 –97 –87 –80 – ...

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... DG534A/538A Vishay Siliconix – – V– EN I/O Decode V L V– REF REF * * V+ I/O V– EN *Typical all Readback (A , EN) pins X www.vishay.com V– Decode Latch Tri-State Buffer V V REF REF V– V REF 8 REF REF REF Document Number: 70069 S-05734—Rev. G, 29-Jan-02 L ...

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... S-05734—Rev. G, 29-Jan- V– = – 100 100 100 120 V– = – 100 120 –100 –80 25_C –60 –40 –55_C – DG534A/538A Vishay Siliconix Leakage vs. Temperature V– = – D(on) I D(off) I S(off) –40 – Temperature (_C) r vs. V–, V+ DS(on – –6 –5 –4 – ...

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... DG534A/538A Vishay Siliconix Adjacent Input Crosstalk vs. Frequency –100 V– = – –80 R PLCC –60 –40 – – Frequency (MHz) All Hostile Crosstalk vs. Frequency –100 –80 DIP – V– = –3 V – – – Frequency (MHz) Differential Crosstalk vs. Frequency –100 –80 – V– = –3 V – ...

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... BBM 100 60 80 100 120 t MPW Write Data Don’t Care t t MPW Device Data* Out FIGURE 1. DG534A/538A Vishay Siliconix Transition Time vs. Temperature t TRANS 75 –40 – Temperature (_C) New Data Don’t Care Hi Z Driven Bus t AI 100 120 www.vishay.com 9 ...

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... DG534A/538A Vishay Siliconix + – Bn 8/4, 4 I/O GND V– – – 8/4, 4/2 I/O Address Logic GND V– Logic Input –3 V www.vishay.com 10 Logic Input 100 nF t < < OUT 100 nF FIGURE 2. EN, CS, CS, Turn On/Off Time + Logic Input 10 mF 100 nF t <20 ns ...

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... Logic Input 100 nF t < < 100 100 1000 100 nF FIGURE 5. Charge Injection DG534A/538A Vishay Siliconix A 50 Turning Off Turning On BBM Interval V O Transition Time (t ) TRANS OUT DV is the measured voltage error due to OUT charge injection. The charge injection in Cou lombs OUT ...

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... DG534A/538A Vishay Siliconix + 8/4 or 4/2 = Logic “0” log X TALK(AH) 10 Note any other one channel on. A1 FIGURE 7. All Hostile Crosstalk Sn–1 S n– Sn – log log V TALK(AI FIGURE 9. Adjacent Input Crosstalk www.vishay.com 12 + – S 8/ GND V– –3 V FIGURE 6. Bandwidth ...

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... HP4192A Impedance Analyzer or Equivalent I/O WR GND FIGURE 12. Off State Input/Output Capacitance Allowable Operating Voltage 14 Area 13 (Note –4 –3 –2 –1 Negative Supply Voltage V– (Volts) FIGURE 13. DG534A/538A Vishay Siliconix Meter HP4192A D Impedance B Analyzer or Equivalent V– –3 V Positive Supply Voltage V+ (Volts) www.vishay.com 13 ...

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... DG534A/538A Vishay Siliconix Pin Number Symbol DG534ADJ – – A4 4/2 7 8/4 – 11, 10, – I – – V– GND Device Description The DG534A/538A D/CMOS wideband multiplexers offer single-ended or differential functions. A 8/4 or 4/2 logic input pin selects the single-ended or differential mode. To meet the high dynamic performance demands of video, high definition TV, digital data routing (in excess of 100 Mbps), etc ...

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... Interfacing Logic interfacing is easily accomplished. Comprehensive addressing and control functions are incorporated in the design. The V pin permits interface to various logic types. The device L is primarily designed to be TTL or CMOS logic compatible with +5 V applied to V simply by increasing V DG534A/538A Vishay Siliconix + ...

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... DG534A/538A Vishay Siliconix A typical switching threshold versus V These devices feature an address readback (Tally) facility, whereby the last address written to the device may be output to the system. This allows improved status monitoring and hand shaking without additional external components. This function is controlled by the I/O pin, which directly addresses the tri-state buffers connected to the EN and address pins ...

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... Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’ ...