M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 

Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
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Features
Supply voltage
– V
= 2.7 V to 3.6 V for program, erase
DD
and read
– V
= V
= 2.4 V to 3.6 V for I/O
DDQ
DDQIN
buffers
– V
= 12 V for fast program (optional)
PP
High performance
– Access times: 70, 80 ns
– 56 MHz effective zero wait-state burst read
– Synchronous burst read
– Asynchronous page read
Hardware block protection
– WP pin for write protect of the 4 outermost
parameter blocks and all main blocks
– RP pin for write protect of all blocks
Optimized for FDI drivers
– Fast program / erase suspend latency
time < 6 µs
– Common Flash interface
Memory blocks
– 8 parameters blocks (top or bottom)
– 31 main blocks
Low power consumption
– 5 µA typical deep power-down
– 60 µA typical standby for M58BW016DT/B
150 µA typical standby for M58BW016FT/B
– Automatic standby after asynchronous read
Electronic signature
– Manufacturer code: 20h
– Top device code: 8836h
– Bottom device code: 8835h
100 K write/erase cycling + 20 years data
retention (minimum)
High reliability level with over 1 M write/erase
cycling sustained
®
ECOPACK
packages available
March 2008
M58BW016DB M58BW016DT
M58BW016FT M58BW016FB
16 Mbit (512 Kbit x 32, boot block, burst)
3 V supply Flash memories
LBGA80 10 × 12 mm
Rev 17
PQFP80 (T)
LBGA
1/70
www.numonyx.com
1

M58BW016DB80T3F Summary of contents

  • Page 1

    ... K write/erase cycling + 20 years data retention (minimum) ■ High reliability level with over 1 M write/erase cycling sustained ® ■ ECOPACK packages available March 2008 M58BW016DB M58BW016DT M58BW016FT M58BW016FB 16 Mbit (512 Kbit x 32, boot block, burst supply Flash memories LBGA80 10 × Rev 17 PQFP80 (T) LBGA 1/70 www.numonyx.com 1 ...

  • Page 2

    Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.1.7 3.1.8 3.1.9 3.1.10 3.2 Synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    ... Contents 5.6 Program suspend status (bit 5.7 Block protection status (bit Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Appendix A Common Flash interface (CFI Appendix B Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...

  • Page 5

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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    ... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 1 Description The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB are 16-Mbit non- volatile Flash memories that can be erased electrically at the block level and programmed in-system on a double-word basis using supply down to 2.4 V for the input and output buffers. Optionally ...

  • Page 8

    Description Figure 1. Logic diagram 8/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DDQ V DDQIN V PP A0-A18 M58BW016DT M58BW016DB RP M58BW016FT M58BW016FB SSQ DQ0-DQ31 R AI11201b ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 1. Signal names Signal A0-A18 DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 DDQ V DDQIN SSQ NC DU Description Address inputs ...

  • Page 10

    Description Figure 2. PQFP connections (top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 10/70 M58BW016DT, M58BW016DB, ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 3. LBGA connections (top view through package A15 B A16 C A17 D DQ3 E V DDQ F V SSQ G V DDQ H DQ13 I DQ15 J V DDQIN 1.1 Block protection ...

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    Description Table 2. M58BW016DT and M58BW016FT top boot block addresses # ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 3. M58BW016DB and M58BW016FB bottom boot block addresses # ...

  • Page 14

    Signal descriptions 2 Signal descriptions See Figure 1: Logic connected to this device. 2.1 Address inputs (A0-A18) The address inputs are used to select the cells to access in the memory array during bus operations either to read or to ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 2.5 Output Disable (GD) The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD the outputs are driven by the Output Enable. When Output Disable, GD ...

  • Page 16

    Signal descriptions 2.9 Burst Clock (K) The Burst Clock used to synchronize the memory with the external bus during synchronous burst read operations. Bus signals are latched on the active edge of the Clock. The Clock can be ...

  • Page 17

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 2.14 Output supply voltage (V The output supply voltage, V program and erase) used for DQ0-DQ31 when used as outputs. 2.15 Input supply voltage (V The input supply voltage GD A0-A18 ...

  • Page 18

    Bus operations 3 Bus operations Each bus operation that controls the memory is described in this section, see Table 5 and Table 6 the burst configuration register; the bits in this register are described at the end of this section. ...

  • Page 19

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.1.3 Asynchronous page read Asynchronous page read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. ...

  • Page 20

    Bus operations 3.1.7 Standby mode When Chip Enable is High, V Standby mode, the power consumption is reduced to the standby level and the Data inputs/outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 5. Asynchronous read electronic signature operation Code Manufacturer Device Burst configuration register 1. BCR = Burst configuration register. 3.2 Synchronous bus operations For synchronous bus operations refer to 3.2.1 Synchronous burst read Synchronous burst read ...

  • Page 22

    Bus operations Valid Data Ready may be configured (by bit M8 of burst configuration register valid immediately at the valid clock edge or one data cycle before the valid clock edge. Synchronous burst read will be suspended if ...

  • Page 23

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.3 Burst configuration register The burst configuration register is used to configure the type of bus access that the memory will perform. The burst configuration register is set through the command interface and will retain its ...

  • Page 24

    Bus operations 3.3.6 Valid clock edge bit (M6) The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, during synchronous burst read operations. When the valid clock edge bit is ’0’ the falling ...

  • Page 25

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 7. Burst configuration register Bit M15 M14 M13-M11 M10 M9 M8 Valid data ready M7 M6 Valid clock edge M5-M4 M3 M2- latencies can be calculated as: (t number from ...

  • Page 26

    Bus operations Table 8. Burst type definition Starting address sequential interleaved 0 0 0-1-2-3 0-1-2 1-2-3-0 1-0-3 2-3-0-1 2-3-0 3-0-1-2 3-2-1 – – 0 ...

  • Page 27

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 4. Example burst configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 5. Example burst configuration X-2-2 ADD VALID L DQ 5-2-2-2 ...

  • Page 28

    ... Read Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area. One bus write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations, depending on the address specified, read from the common Flash interface memory area ...

  • Page 29

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 4.4 Read Status Register command The Read Status Register command is used to read the status register. One bus write cycle is required to issue the Read Status Register command. Once the command is issued subsequent ...

  • Page 30

    Command interface 4.6 Block Erase command The Block Erase command can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is ...

  • Page 31

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 4.8 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a program or erase operation. The command will only be accepted during a program or erase operation. It can be issued at any time ...

  • Page 32

    Command interface 4.10 Set Burst Configuration Register command The Set Burst Configuration Register command is used to write a new value to the burst configuration control register which defines the burst length, type, X and Y latencies, synchronous/asynchronous read mode ...

  • Page 33

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 10. Program, erase times and program, erase endurance cycles Parameters Parameter Block (64 Kbits) Program Main Block (512 Kbits) Program Parameter Block Erase Main Block Erase Program Suspend Latency time Erase Suspend Latency time Program/Erase ...

  • Page 34

    Status register 5 Status register The Status register provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. They are output on DQ7-DQ0. To read ...

  • Page 35

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 5.3 Erase status (bit 5) The erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The erase status bit should be read once the ...

  • Page 36

    Status register 5.6 Program suspend status (bit 2) The program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. The program suspend status should only be considered valid when the program/erase controller ...

  • Page 37

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 6 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated ...

  • Page 38

    DC and AC parameters 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from ...

  • Page 39

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 7. AC measurement load circuit Table 14. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT ° MHz Sampled only, not 100% tested. 1.3 ...

  • Page 40

    DC and AC parameters Table 15. DC characteristics Symbol Parameter I Input Leakage current LI I Output Leakage current LO I Supply current (Random Read) DD (1) I Supply current (Power-up) DDP-UP I Supply current (Burst Read) DDB Supply current ...

  • Page 41

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 8. Asynchronous bus read AC waveforms A0-A18 DQ0-DQ31 . Table 16. Asynchronous bus read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV ...

  • Page 42

    DC and AC parameters Figure 9. Asynchronous latch controlled bus read AC waveforms A0-A18 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous latch controlled bus read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Chip ...

  • Page 43

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 10. Asynchronous page read AC waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous page read AC characteristics Symbol t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see ...

  • Page 44

    DC and AC parameters Figure 11. Asynchronous write AC waveforms 44/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...

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    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 12. Asynchronous latch controlled write AC waveforms DC and AC parameters 45/70 ...

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    DC and AC parameters Table 19. Asynchronous write and latch controlled write AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH ...

  • Page 47

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge) 1. The M58BW016F first data output is synchronized with the clock’s active edge, while the M58BW016D first data output is not synchronized with the ...

  • Page 48

    DC and AC parameters Table 20. Synchronous burst read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid t BHKH Clock Edge Burst Address Advance Low to Valid t BLKH Clock Edge ...

  • Page 49

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 15. Synchronous burst read - continuous - valid data ready output K (1) Output Valid Data Ready = Valid Low during valid clock edge Valid output ...

  • Page 50

    DC and AC parameters Figure 17. Reset, power-down and power-up AC waveforms - control pins low tVDHPH VDD, VDDQ Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling ...

  • Page 51

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 19. Power supply slope specification Voltage VDHH VDH 1. Please refer to the application note AN2601. Table 21. Power supply AC and DC characteristics Symbol V Minimum value of power supply DH V Maximum value ...

  • Page 52

    Package mechanical 8 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK packages. ECOPACK marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to ...

  • Page 53

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data Symbol millimeters Typ Min Max ...

  • Page 54

    Package mechanical Figure 21. LBGA80 10 × × 10 active ball array pitch, package outline Drawing is not to scale. Table 24. LBGA80 10 × × ...

  • Page 55

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 9 Ordering information Table 25. Ordering information scheme Example: Device type M58 Architecture B = Burst mode Operating voltage 2 3 Device function 016D = 16-Mbit (x ...

  • Page 56

    ... Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...

  • Page 57

    ... Number (n-1) of blocks of identical size; n=31 00h 00h Erase block region information x 256 bytes per erase block (64 Kbytes) 01h 07h Number (n-1) of blocks of identical size; n=8 00h 20h Erase block region information x 256 bytes per erase block (8 Kbytes) 00h Common Flash interface (CFI) Description Description 57/70 ...

  • Page 58

    ... Common Flash interface (CFI) Table 30. Extended query information Address Address offset A18-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h 3Fh 58/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Data (Hex) 50h " ...

  • Page 59

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Appendix B Flowcharts Figure 22. Program flowchart and pseudocode Start Write 40h Write Address & Data Read Status Register YES YES YES YES End ...

  • Page 60

    Flowcharts Figure 23. Program suspend & resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block Write D0h Program Continues 60/70 M58BW016DT, M58BW016DB, ...

  • Page 61

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 24. Block erase flowchart and pseudocode Start Write 20h Write Block Address & D0h Read Status Register YES YES b4 and YES ...

  • Page 62

    Flowcharts Figure 25. Erase suspend & resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program Write D0h Erase Continues 62/70 ...

  • Page 63

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 26. Power-up sequence followed by synchronous burst read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '1' Set Burst Configuration Register Command: – ...

  • Page 64

    Flowcharts Figure 27. Command interface and program/erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B 64/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO YES NO 70h YES READ ...

  • Page 65

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 28. Command interface and program/erase controller flowchart ( 60h YES NO FFh SET BCR SET_UP YES NO 03h YES Flowcharts D AI03836b 65/70 ...

  • Page 66

    Flowcharts Figure 29. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY 66/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE ...

  • Page 67

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 30. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS Flowcharts C PROGRAM READY NO NO READ B0h ...

  • Page 68

    Revision history 10 Revision history Table 31. Document revision history Date Version January-2001 05-Jun-2001 15-Jun-2001 17-Jul-2001 17-Dec-2001 17-Jan-2002 30-Aug-2002 4-Sep-2002 13-May-2003 16-Oct-2003 03-Mar-2005 06-Sep-2005 3-Mar-2006 16-Jun-2006 68/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 01 First Issue. 02 Major rewrite and restructure. 03 ...

  • Page 69

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 31. Document revision history (continued) Date Version 09-Nov-2006 24-Nov-2006 05-Oct-2007 16-Jan-2008 12-Mar-2008 26-Mar-2008 LBGA80 package added (see M58BW016FT and M58BW016FB behavior in Burst mode specified under Section 3.2.1: Synchronous burst and I ...

  • Page 70

    ... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...