M58BW016DB80T3F Micron Technology Inc, M58BW016DB80T3F Datasheet - Page 14

• Manufacturer Part Number: M58BW016DB80T3F
• Manufacturer: Micron Technology Inc

Specifications of M58BW016DB80T3F

• Lead Free Status / Rohs Status: Not Compliant

Signal descriptions
2
2.1
2.2
2.3
2.4
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Signal descriptions
See
connected to this device.
Address inputs (A0-A18)
The address inputs are used to select the cells to access in the memory array during bus
operations either to read or to program data. During bus write operations they control the
commands sent to the command interface of the program/erase controller. Chip Enable
must be Low when selecting the addresses.
The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,
whichever occurs first, in a read operation.The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation.
The address latch is transparent when Latch Enable is Low, V
latched in an erase or program operation.
Data inputs/outputs (DQ0-DQ31)
The data inputs/outputs output the data stored at the selected address during a bus read
operation, or are used to input the data during a program operation. During bus write
operations they represent the commands sent to the command interface of the
program/erase controller. When used to input data or write commands they are latched on
the rising edge of Write Enable or Chip Enable, whichever occurs first.
When Chip Enable and Output Enable are both Low, V
data bus outputs data from the memory array, the electronic signature, the CFI information
or the contents of the status register. The data bus is high impedance when the device is
deselected with Chip Enable at V
Reset/Power-down at V
DQ31 are at V
Chip Enable (E)
The Chip Enable, E, input activates the memory control logic, input buffers, decoders and
sense amplifiers. Chip Enable, E, at V
consumption to the standby level.
Output Enable (G)
The Output Enable, G, gates the outputs through the data output buffers during a read
operation, when Output Disable GD is at V
are high impedance independently of Output Disable.
Figure 1: Logic
IL
.
diagram, and
IL
. The status register content is output on DQ0-DQ7 and DQ8-
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
IH
Table 1: Signal names
, Output Enable at V
IH
deselects the memory and reduces the power
IH
. When Output Enable G is at V
IL
IH
, and Output Disable is at V
for a brief overview of the signals
, Output Disable at V
IL
. The address is internally
IH
, the outputs
IL
or
IH,
the