M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 

Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
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Page 20/70

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Bus operations
3.1.7
Standby mode
When Chip Enable is High, V
Standby mode, the power consumption is reduced to the standby level and the Data
inputs/outputs pins are placed in the high impedance state regardless of Output Enable,
Write Enable or Output Disable inputs.
3.1.8
Automatic low power mode
If there is no change in the state of the bus for a short period of time during asynchronous
bus read operations the memory enters auto low power mode where the internal supply
current is reduced to the auto-standby supply current. The data inputs/outputs will still
output data if a bus read operation is in progress.
Automatic low power is only available in asynchronous read modes.
3.1.9
Power-down mode
The memory is in power-down when Reset/Power-down, RP, is at V
consumption is reduced to the power-down level and the outputs are high impedance,
independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable,
W, inputs.
3.1.10
Electronic signature
Two codes identifying the manufacturer and the device can be read from the memory
allowing programming equipment or applications to automatically match their interface to
the characteristics of the memory. The electronic signature is output by giving the Read
Electronic Signature command. The manufacturer code is output when all the address
inputs are at V
. The device code is output when A1 is at V
IL
are at V
(see
Table 5: Asynchronous read electronic signature
IL
Memory Array command to return to read mode.
Table 4.
Asynchronous bus operations
Bus operation
Asynchronous bus read
Asynchronous latch
controlled bus read
Asynchronous page read
Asynchronous bus write
Asynchronous latch
controlled bus write
Output Enable, G
Output Disable, GD
Standby
Reset/power-down
1. X = don’t care.
20/70
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
, and the Program/Erase controller is idle, the memory enters
IH
(1)
Step
E
G
GD
V
V
V
IL
IL
IH
Address Latch V
V
V
IL
IH
IH
Read
V
V
V
IL
IL
IH
V
V
V
IL
IL
IH
V
V
X
IL
IH
Address Latch V
V
V
IL
IL
IH
Write
V
V
X
IL
IH
V
V
V
IL
IH
IH
V
V
V
IL
IL
IL
V
X
X
IH
X
X
X
. The power
IL
and all the other address pins
IH
operation). Issue a Read
W
RP
L
A0-A18
DQ0-DQ31
V
V
V
Address Data output
IH
IH
IL
V
V
V
Address
High-Z
IL
IH
IL
V
V
V
X
Data output
IH
IH
IH
V
V
X
Address Data output
IH
IH
V
V
V
Address
Data input
IL
IH
IL
V
V
V
Address
High-Z
IH
IH
IL
V
V
V
X
Data input
IL
IH
IH
V
V
X
X
High-Z
IH
IH
V
V
X
X
High-Z
IH
IH
X
V
X
X
High-Z
IH
X
V
X
X
High-Z
IL