M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 


Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
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Bus operations
Valid Data Ready may be configured (by bit M8 of burst configuration register) to be valid
immediately at the valid clock edge or one data cycle before the valid clock edge.
Synchronous burst read will be suspended if Burst Address Advance, B, goes High, V
If Output Enable is at V
If Output Enable, G, is at V
Advance, B, is at V
K valid edge.
The synchronous burst read timing diagrams and AC characteristics are described in the AC
and DC parameters section. See
Table
20.
3.2.2
Synchronous burst read suspend
During a synchronous burst read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid synchronous burst read operation is suspended when both Output Enable and Burst
Address Advance are High, V
burst counter and the Output Enable going High, V
synchronous burst read operation can be resumed by setting Output Enable Low.
Table 6.
Synchronous burst read bus operations
Bus operation
Synchronous
burst read
1. X = don't care, V
IL
2. M15 = 0, bit M15 is in the burst configuration register.
3. T = transition, see M6 in the burst configuration register for details on the active edge of K.
22/70
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
and Output Disable is at V
IL
or Output Disable, GD, is at V
IH
the internal Burst Address counter is incremented at each Burst Clock
IL
Figure
13,
Figure
. The Burst Address Advance going High, V
IH
Step
E
G
Address Latch
V
V
IL
IH
Read
V
V
IL
IL
Read Suspend
V
V
IL
IH
Read Resume
V
V
IL
IL
Burst Address
V
V
IL
IH
Advance
Read Abort, E
V
X
IH
Read Abort, RP
X
X
or V
.
IH
, the last data is still valid.
IH
, but the Burst Address
IL
14,
Figure 15
and
Figure
16, and
, stops the
IH
, inhibits the data outputs. The
IH
(1)(2)
A0-A18
(3)
GD RP K
L
B
DQ0-DQ31
X
V
T
V
X
Address input
IH
IL
V
V
T
V
V
Data output
IH
IH
IH
IL
X
V
X
V
V
IH
IH
IH
V
V
T
V
V
Data output
IH
IH
IH
IL
X
V
T
V
V
IH
IH
IL
X
V
X
X
X
IH
X
V
X
X
X
IL
.
IH
High-Z
High-Z
High-Z
High-Z