M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 


Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Page 24/70

Download datasheet (2Mb)Embed
PrevNext
Bus operations
3.3.6
Valid clock edge bit (M6)
The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, during
synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of
the clock is the active edge; when the valid clock edge bit is ’1’ the rising edge of the clock is
active.
3.3.7
Wrap burst bit (M3)
The burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or
overcome the boundary (no wrap). The wrap burst bit is used to select between wrap and no
wrap. When the wrap burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst
read does not wrap.
3.3.8
Burst length bit (M2-M0)
The burst length bits set the maximum number of double-words that can be output during a
synchronous burst read operation before the address wraps. Burst lengths of 4 or 8 are
available for both the sequential and interleaved burst types, and a continuous burst is
available for the sequential type.
Table 7: Burst configuration register
the memory accepts;
from a given starting address for each length.
If either a continuous or a no wrap burst read has been initiated the device will output data
synchronously. Depending on the starting address, the device activates the valid data ready
output to indicate that a delay is necessary before the data is output. If the starting address
is aligned to an 8 double-word boundary, the continuous burst mode will run without
activating the valid data ready output. If the starting address is not aligned to an 8 double-
word boundary, valid data ready is activated to indicate that the device needs an internal
delay to read the successive words in the array.
M10, M5 and M4 are reserved for future use.
24/70
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
gives the valid combinations of the burst length bits that
Table 8: Burst type
definition, gives the sequence of addresses output