HEF4557BP NXP Semiconductors, HEF4557BP Datasheet

HEF4557BP

Manufacturer Part Number
HEF4557BP
Description
Manufacturer
NXP Semiconductors
Type
Not Requiredr
Datasheet

Specifications of HEF4557BP

Technology
CMOS
Number Of Elements
1
Number Of Bits
64
Logic Family
4000
Logical Function
Shift Register
Operating Supply Voltage (typ)
3.3/5/9/12V
Package Type
PDIP
Propagation Delay Time
480ns
Operating Temp Range
-40C to 85C
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HEF4557BP
Manufacturer:
PHI
Quantity:
6 249
1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF4557BP
HEF4557BT
Ordering information
Package
Name
DIP16
SO16
40
The HEF4557B is a static clocked serial shift register whose length may be programmed
to be any number of bits between 1 and 64. The number of bits selected is equal to the
sum of the subscripts of the enabled length control inputs (L1, L2, L4, L8, L16, and L32)
plus one. Serial data may be selected from the DA or DB data inputs with the A/B select
input. This feature is useful for recirculation purposes. Information on DA or DB is shifted
into the first register position and all the data in the register is shifted one position to the
right on the LOW to HIGH transition of CP0 while CP1 is LOW or on the HIGH to LOW
transition of CP1 while CP0 is HIGH. A HIGH on master reset (MR) resets the register and
forces Q to LOW and Q to HIGH, independent of the other inputs.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
°
C to +85
HEF4557B
1-to-64 bit variable length shift register
Rev. 05 — 16 December 2009
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Industrial
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
°
C
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

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HEF4557BP Summary of contents

Page 1

... Table 1. Ordering information − ° All types operate from +85 Type number Package Name Description HEF4557BP DIP16 plastic dual in-line package; 16 leads (300 mil) HEF4557BT SO16 plastic small outline package; 16 leads; body width 3.9 mm power supply range referenced ° C Product data sheet ...

Page 2

A FF1 CP1 CP0 MR FF60 FF57 Fig 1. Logic diagram L32 L16 FF32 FF33 ...

Page 3

... NXP Semiconductors 9 A CP1 5 CP0 4 Fig 2. Functional diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description table Symbol Pin L1, L2, L4, L8, L16, L32 2, 1, 15, 14, 13 CP0 4 CP1 5 DA A/B 9 HEF4557B_5 Product data sheet 1-to-64 bit variable length shift register ...

Page 4

... NXP Semiconductors Table 2. Pin description table …continued Symbol Pin Functional description [1] Table 3. Function table Inputs MR A [1] The moment D appears at Q depends on the bit-length shown don’t care; ↑ = positive-going transition; ↓ = negative-going transition; D Table 4. Bit-length select function table L32 L16 L16 continue to increment in a binary count with L32 LOW ...

Page 5

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current DD T storage temperature stg ...

Page 6

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I HIGH-level output current OH I LOW-level output current OL I input leakage current I I supply current ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW CP0, CP1 PHL propagation delay see Figure see t LOW to HIGH CP0, CP1 PLH propagation delay see Figure see t transition time see Figure set-up time ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t recovery time MR input; rec L1 to L32 = LOW; see Figure 5 MR input; L32 = HIGH f maximum see Figure 5 max frequency [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C [2] The set-up, hold, and recovery times vary with the minimum number of bits selected ...

Page 9

... NXP Semiconductors 12. Waveforms V I CP0 input (CP1 LOW CP1 input (CP0 HIGH input output output V OL For measurement points see Logic levels: V and V are typical output voltage levels that occur with the output load Fig 4. Propagation delays HEF4557B_5 Product data sheet ...

Page 10

... NXP Semiconductors V I CP0 input (CP1 = CP1 input (CP0 = DA, DB input A/B input input 0 V Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area indicates where data can change for predictable performance. For measurement points see Fig 5 ...

Page 11

... NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 11. Definitions for test circuit: Device Under Test (DUT Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 6. Test circuit for switching times Table 11. ...

Page 12

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors 14. Revision history Table 12. Revision history Document ID Release date HEF4557B_5 20091216 • Modifications: Section 9 “Recommended operating conditions” HEF4557B_4 20090916 HEF4557B_CNV_3 19950101 HEF4557B_CNV_2 19950101 HEF4557B_5 Product data sheet 1-to-64 bit variable length shift register Data sheet status Change notice Product data sheet - Δ ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...

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