IDT6116SA45SOG IDT, Integrated Device Technology Inc, IDT6116SA45SOG Datasheet - Page 9

• Manufacturer Part Number: IDT6116SA45SOG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT6116SA45SOG

• Density: 16Kb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 11b
• Package Type: SOIC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 100mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Word Size: 8b
• Number Of Words: 2K
• Lead Free Status / Rohs Status: Compliant

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
ADDRESS
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. t
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
DATA
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
DATA
to turn off and data to be placed on the bus for the required t
is the specified t
DATA
WR
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
OUT
WE
WE
CS
CS
IN
IN
WP
. For a CS controlled write cycle, OE may be LOW with no degradation to t
PREVIOUS DATA VALID
t
AS
t
AS
DW
t
WHZ
(4)
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse
(6)
t
AW
t
WC
t
AW
t
6.42
WP (7)
t
WC
t
9
CW
t
t
Military, Commercial, and Industrial Temperature Ranges
DW
DW
DATA VALID
CW
.
DATA VALID
t
WR
t
(3)
DH
t
OW
t
WR
(6)
(3)
WP
or (t
t
WHZ
DH
+ t
DW
DATA
VALID
(1,2,3,5,7)
t
) to allow the I/O drivers
(1,2,5,7)
CHZ
(6)
(4)
3089 drw 09
3089 drw 10
,
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