MC74HC595AN ON Semiconductor, MC74HC595AN Datasheet

MC74HC595AN

Manufacturer Part Number
MC74HC595AN
Description
Manufacturer
ON Semiconductor
Type
Not Requiredr
Datasheet

Specifications of MC74HC595AN

Technology
CMOS
Number Of Elements
1
Number Of Bits
8
Logic Family
HC
Logical Function
Shift Register
Operating Supply Voltage (typ)
2.5/3.3/5V
Output Type
3-State
Package Type
PDIP
Propagation Delay Time
225ns
Operating Temp Range
-55C to 125C
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
16
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC74HC595AN
Manufacturer:
MOT
Quantity:
12 000
Part Number:
MC74HC595AN
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC74HC595AN
Quantity:
525
Part Number:
MC74HC595ANG
Manufacturer:
ON
Quantity:
2 000
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High−Performance Silicon−Gate CMOS
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
CMOS MPUs and MCUs.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2008
January, 2009 − Rev. 11
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74HC595A consists of an 8−bit shift register and an 8−bit
The HC595A directly interfaces with the SPI serial data port on
Standard No. 7A
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Pb−Free Packages are Available*
− Improved Propagation Delays
− 50% Lower Quiescent Power
− Improved Input Noise and Latchup Immunity
1
16
16
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
16
1
(Note: Microdot may be in either location)
1
1
A
WL, L
YY, Y
WW, W
G, G
ORDERING INFORMATION
http://onsemi.com
CASE 751B
CASE 948F
DT SUFFIX
TSSOP−16
CASE 648
N SUFFIX
D SUFFIX
SOIC−16
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
16
16
1
1
MC74HC595AN
DIAGRAMS
16
MC74HC595A/D
MARKING
1
AWLYYWWG
HC595AG
AWLYWW
ALYWG
595A
HC
G

Related parts for MC74HC595AN

MC74HC595AN Summary of contents

Page 1

... Year WW Work Week Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 1 MARKING DIAGRAMS 16 MC74HC595AN AWLYYWWG 1 16 HC595AG AWLYWW 595A ALYWG G 1 Publication Order Number: ...

Page 2

... RESET H GND ORDERING INFORMATION Device MC74HC595AN MC74HC595ANG MC74HC595AD MC74HC595ADG MC74HC595ADR2 MC74HC595ADR2G MC74HC595ADT MC74HC595ADTR2 MC74HC595ADTR2G MC74HC595AFEL MC74HC595AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. ...

Page 3

... Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 4

... Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

... C Power Dissipation Capacitance (Per Package Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input t Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 6

Serial Input A Reset Operation Reset shift register L X Shift data into shift H D register Shift register remains H X unchanged Transfer shift register H X contents to latch register Latch register remains X X unchanged Enable parallel ...

Page 7

SHIFT 90% 50% CLOCK 10 1/f max t t PLH PHL 90% OUTPUT 50 10 TLH THL Figure 1. LATCH 50% CLOCK t t PLH PHL 90 ...

Page 8

OUTPUT 13 ENABLE LATCH 12 CLOCK SERIAL 14 DATA INPUT A SHIFT 11 CLOCK 10 RESET EXPANDED LOGIC DIAGRAM ...

Page 9

SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT SQ H NOTE: implies that the output ...

Page 10

0.25 (0.010) −A − −B − −T − SEATING PLANE 0.25 (0.010 PACKAGE DIMENSIONS PDIP−16 ...

Page 11

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

Related keywords