HEF4021BT NXP Semiconductors, HEF4021BT Datasheet

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HEF4021BT

Manufacturer Part Number
HEF4021BT
Description
Manufacturer
NXP Semiconductors
Type
Not Requiredr
Datasheet

Specifications of HEF4021BT

Technology
CMOS
Number Of Elements
1
Number Of Bits
8
Logic Family
4000
Logical Function
Shift Register
Operating Supply Voltage (typ)
3.3/5/9/12V
Output Type
Standard
Package Type
SO
Propagation Delay Time
250ns
Operating Temp Range
-40C to 125C
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Compliant

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1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from 40 C to +125 C.
Type number
HEF4021BP
HEF4021BT
Ordering information
Package
Name
DIP16
SO16
The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a
synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH
parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered
parallel outputs from the last three stages (Q5 to Q7).
Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct
(CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is
HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first
register position and all the data in the register is shifted one position to the right on the
LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant
of slower rise and fall times.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over both the industrial ( 40 C to +85 C) and automotive ( 40 C to
+125 C) temperature ranges.
I
I
I
I
I
I
I
HEF4021B
8-bit static shift register
Rev. 06 — 27 November 2009
Tolerant of slower rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Industrial and automotive
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

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HEF4021BT Summary of contents

Page 1

... Table 1. Ordering information All types operate from +125 C. Type number Package Name Description HEF4021BP DIP16 plastic dual in-line package; 16 leads (300 mil) HEF4021BT SO16 plastic small outline package; 16 leads; body width 3.9 mm power supply range referenced another input Product data sheet ...

Page 2

... NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram Fig 2. Logic diagram HEF4021B_6 Product data sheet SD/ SHIFT REGISTER 10 CP 8-BITS Rev. 06 — 27 November 2009 HEF4021B 8-bit static shift register 001aae608 001aae610 © NXP B.V. 2009. All rights reserved ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 12 13, 14,15 Functional description [1] Table 3. Function table Number of clock Inputs transitions CP Serial operation HEF4021B_6 Product data sheet HEF4021B 001aae609 Description buffered parallel output from the last three stages ...

Page 4

... NXP Semiconductors [1] Table 3. Function table …continued Number of clock Inputs transitions CP 8 Parallel operation X [ HIGH voltage level LOW voltage level don’t care; = LOW to HIGH clock transition; data n = data (HIGH or LOW) on the DS input at the n 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions V HIGH-level I < input voltage V LOW-level I < input voltage V HIGH-level I < output voltage V LOW-level I < output voltage I HIGH-level output current LOW-level output current V = 0.5 V ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics for test circuit see SS amb Symbol Parameter t LOW to HIGH PLH propagation delay t transition time t t set-up time su t hold time h t pulse width W t recovery time rec f maximum clock clk(max) frequency [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C ...

Page 7

... NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms INPUT Qn OUTPUT Fig 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times INPUT INPUT V SS Fig 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS. ...

Page 8

... NXP Semiconductors INPUT INPUT INPUT V SS Set-up times and hold times are shown as positive values but may be specified as negative values; Measurement points are given in Fig 6. Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL. ...

Page 9

... NXP Semiconductors a. Input waveform b. Test circuit Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 7. Test circuit for measuring switching times Table 10. ...

Page 10

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4021B_6 20091127 • Modifications: Section 9 “Recommended operating HEF4021B_5 20090707 HEF4021B_4 20081110 HEF4021B_CNV_3 19950101 HEF4021B_CNV_2 19950101 HEF4021B_6 Product data sheet Data sheet status Change notice Product data sheet - conditions” values updated. ...

Page 13

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 Revision history ...

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